DE60213520D1 - Halbleiterspeicheranordnung und Informationsanordnung - Google Patents

Halbleiterspeicheranordnung und Informationsanordnung

Info

Publication number
DE60213520D1
DE60213520D1 DE60213520T DE60213520T DE60213520D1 DE 60213520 D1 DE60213520 D1 DE 60213520D1 DE 60213520 T DE60213520 T DE 60213520T DE 60213520 T DE60213520 T DE 60213520T DE 60213520 D1 DE60213520 D1 DE 60213520D1
Authority
DE
Germany
Prior art keywords
arrangement
semiconductor memory
information
memory arrangement
information arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60213520T
Other languages
English (en)
Other versions
DE60213520T2 (de
Inventor
Ken Nakazawa
Ken Sumitani
Haruyasu Fukui
Yasumichi Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE60213520D1 publication Critical patent/DE60213520D1/de
Application granted granted Critical
Publication of DE60213520T2 publication Critical patent/DE60213520T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
DE60213520T 2001-06-28 2002-06-28 Halbleiterspeicheranordnung und Informationsanordnung Expired - Lifetime DE60213520T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001197538 2001-06-28
JP2001197538A JP3815718B2 (ja) 2001-06-28 2001-06-28 半導体記憶装置および情報機器

Publications (2)

Publication Number Publication Date
DE60213520D1 true DE60213520D1 (de) 2006-09-14
DE60213520T2 DE60213520T2 (de) 2007-03-08

Family

ID=19035126

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60213520T Expired - Lifetime DE60213520T2 (de) 2001-06-28 2002-06-28 Halbleiterspeicheranordnung und Informationsanordnung

Country Status (6)

Country Link
US (1) US6549475B2 (de)
EP (1) EP1271551B1 (de)
JP (1) JP3815718B2 (de)
KR (1) KR100479274B1 (de)
DE (1) DE60213520T2 (de)
TW (1) TW584865B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITRM20020369A1 (it) * 2002-07-09 2004-01-09 Micron Technology Inc Architettura a burst per memoria a doppio bus.
FI20035041A0 (fi) * 2003-03-31 2003-03-31 Nokia Corp Menetelmä tiedon tallentamiseksi muistiin, järjestelmä, elektroniikkalaite ja muistikortti
JP4491267B2 (ja) * 2004-04-09 2010-06-30 パナソニック株式会社 不揮発性半導体記憶装置
US8429313B2 (en) * 2004-05-27 2013-04-23 Sandisk Technologies Inc. Configurable ready/busy control
CN102436559B (zh) * 2010-09-29 2016-06-01 联想(北京)有限公司 一种状态切换方法及系统
KR101196911B1 (ko) * 2010-12-30 2012-11-05 에스케이하이닉스 주식회사 반도체 장치 및 이를 이용한 전압 생성 방법
US8614920B2 (en) 2012-04-02 2013-12-24 Winbond Electronics Corporation Method and apparatus for logic read in flash memory
JP5467134B1 (ja) * 2012-09-27 2014-04-09 華邦電子股▲ふん▼有限公司 フラッシュメモリ装置およびメモリ装置の操作方法
KR102529158B1 (ko) 2020-12-31 2023-05-08 (유)태진엔지니어링 선박용 유수분리기를 가진 배출 모니터링 시스템

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
US5224070A (en) * 1991-12-11 1993-06-29 Intel Corporation Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
JP3463912B2 (ja) * 1997-09-09 2003-11-05 シャープ株式会社 フラッシュメモリのライトステートマシンのハードウェアリセット
JP3599541B2 (ja) * 1997-11-27 2004-12-08 シャープ株式会社 不揮発性半導体記憶装置
JP3580702B2 (ja) * 1998-06-03 2004-10-27 シャープ株式会社 不揮発性半導体記憶装置
US6067267A (en) * 1998-08-12 2000-05-23 Toshiba America Electronic Components, Inc. Four-way interleaved FIFO architecture with look ahead conditional decoder for PCI applications
JP3871184B2 (ja) 2000-06-12 2007-01-24 シャープ株式会社 半導体記憶装置

Also Published As

Publication number Publication date
US20030021163A1 (en) 2003-01-30
TW584865B (en) 2004-04-21
JP2003016788A (ja) 2003-01-17
EP1271551A3 (de) 2004-10-20
DE60213520T2 (de) 2007-03-08
EP1271551B1 (de) 2006-08-02
KR100479274B1 (ko) 2005-03-28
KR20030011252A (ko) 2003-02-07
US6549475B2 (en) 2003-04-15
JP3815718B2 (ja) 2006-08-30
EP1271551A2 (de) 2003-01-02

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