DE60211338D1 - Integrierte schaltungsanordnung mit funktionssteuerung - Google Patents

Integrierte schaltungsanordnung mit funktionssteuerung

Info

Publication number
DE60211338D1
DE60211338D1 DE60211338T DE60211338T DE60211338D1 DE 60211338 D1 DE60211338 D1 DE 60211338D1 DE 60211338 T DE60211338 T DE 60211338T DE 60211338 T DE60211338 T DE 60211338T DE 60211338 D1 DE60211338 D1 DE 60211338D1
Authority
DE
Germany
Prior art keywords
integrated circuit
mode
circuit
reconfigurable
modes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60211338T
Other languages
English (en)
Other versions
DE60211338T2 (de
Inventor
T Wingen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE60211338D1 publication Critical patent/DE60211338D1/de
Application granted granted Critical
Publication of DE60211338T2 publication Critical patent/DE60211338T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Information Transfer Systems (AREA)
DE60211338T 2001-05-31 2002-05-29 Integrierte schaltungsanordnung mit funktionssteuerung Expired - Lifetime DE60211338T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US871231 2001-05-31
US09/871,231 US6621293B2 (en) 2001-05-31 2001-05-31 Integrated circuit arrangement with feature control
PCT/IB2002/001915 WO2002097638A2 (en) 2001-05-31 2002-05-29 An integrated circuit arrangement with feature control

Publications (2)

Publication Number Publication Date
DE60211338D1 true DE60211338D1 (de) 2006-06-14
DE60211338T2 DE60211338T2 (de) 2007-02-08

Family

ID=25356985

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60211338T Expired - Lifetime DE60211338T2 (de) 2001-05-31 2002-05-29 Integrierte schaltungsanordnung mit funktionssteuerung

Country Status (6)

Country Link
US (1) US6621293B2 (de)
EP (1) EP1399828B1 (de)
JP (1) JP2004520664A (de)
AT (1) ATE326036T1 (de)
DE (1) DE60211338T2 (de)
WO (1) WO2002097638A2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10105987A1 (de) * 2001-02-09 2002-08-29 Infineon Technologies Ag Datenverarbeitungsvorrichtung
US6742057B2 (en) * 2001-05-31 2004-05-25 Koninklijke Philips Electronics N.V. Automatic upgradeable UART circuit arrangement
US7501703B2 (en) * 2003-02-28 2009-03-10 Knowles Electronics, Llc Acoustic transducer module
US7155644B2 (en) * 2003-05-08 2006-12-26 Micron Technology, Inc. Automatic test entry termination in a memory device
JP4626142B2 (ja) * 2003-11-18 2011-02-02 株式会社日立製作所 装置およびそれを用いたデータ処理方法
US7975094B2 (en) * 2004-04-15 2011-07-05 Marvell International Technology Ltd. Programmable I/O interface
US8244951B2 (en) 2008-09-25 2012-08-14 Intel Corporation Method and apparatus to facilitate system to system protocol exchange in back to back non-transparent bridges
US8966657B2 (en) * 2009-12-31 2015-02-24 Intel Corporation Provisioning, upgrading, and/or changing of hardware
KR101578575B1 (ko) * 2010-03-24 2015-12-17 세키스이가가쿠 고교가부시키가이샤 접착제 조성물, 접착 테이프, 반도체 웨이퍼의 처리 방법 및 tsv 웨이퍼의 제조 방법
US9736086B1 (en) * 2011-04-29 2017-08-15 Altera Corporation Multi-function, multi-protocol FIFO for high-speed communication
US9930050B2 (en) * 2015-04-01 2018-03-27 Hand Held Products, Inc. Device management proxy for secure devices
CN108415874B (zh) * 2018-05-02 2024-02-06 武汉华讯国蓉科技有限公司 一种基于eim总线的接口扩展设备和方法
CN111078603B (zh) * 2019-10-30 2021-08-20 苏州浪潮智能科技有限公司 一种多节点设备内部串口访问的控制方法和系统
CN111090602B (zh) * 2019-12-24 2022-04-15 成都天玙兴科技有限公司 一种uart串口收发自适应方法和系统

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699525A (en) * 1970-11-27 1972-10-17 Honeywell Inf Systems Use of control words to change configuration and operating mode of a data communication system
JP3166193B2 (ja) * 1991-04-23 2001-05-14 株式会社デンソー 半導体集積回路
US6092165A (en) * 1996-08-16 2000-07-18 Unisys Corporation Memory control unit using a programmable shift register for generating timed control signals
US6011407A (en) * 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
JP3953153B2 (ja) * 1997-09-18 2007-08-08 富士通株式会社 プログラマブル・ゲートアレイのコンフィグレーション方法及びプログラマブル・ゲートアレイ装置
US6237054B1 (en) * 1998-09-14 2001-05-22 Advanced Micro Devices, Inc. Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions
EP1061451A3 (de) * 1999-06-17 2004-12-29 Tadiran Telecom Business Systems Ltd. Übertragungssystem, das ein serielles Port mit zwei Betriebsarten hat
JP2001184301A (ja) * 1999-12-27 2001-07-06 Seiko Instruments Inc 画像データ転送方法ならびに装置

Also Published As

Publication number Publication date
WO2002097638A2 (en) 2002-12-05
EP1399828B1 (de) 2006-05-10
WO2002097638A3 (en) 2003-10-23
US6621293B2 (en) 2003-09-16
DE60211338T2 (de) 2007-02-08
EP1399828A2 (de) 2004-03-24
JP2004520664A (ja) 2004-07-08
ATE326036T1 (de) 2006-06-15
US20020181641A1 (en) 2002-12-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL