DE602008006465D1 - Verfahren zur herstellung eines drahtteils in einer integrierten elektronischen schaltung - Google Patents
Verfahren zur herstellung eines drahtteils in einer integrierten elektronischen schaltungInfo
- Publication number
- DE602008006465D1 DE602008006465D1 DE602008006465T DE602008006465T DE602008006465D1 DE 602008006465 D1 DE602008006465 D1 DE 602008006465D1 DE 602008006465 T DE602008006465 T DE 602008006465T DE 602008006465 T DE602008006465 T DE 602008006465T DE 602008006465 D1 DE602008006465 D1 DE 602008006465D1
- Authority
- DE
- Germany
- Prior art keywords
- wire portion
- electronic circuit
- integrated electronic
- seed layer
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000000694 effects Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Materials Engineering (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07301401 | 2007-09-26 | ||
PCT/EP2008/062622 WO2009040328A1 (en) | 2007-09-26 | 2008-09-22 | Process for forming a wire portion in an integrated electronic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602008006465D1 true DE602008006465D1 (de) | 2011-06-01 |
Family
ID=40091357
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602008006465T Active DE602008006465D1 (de) | 2007-09-26 | 2008-09-22 | Verfahren zur herstellung eines drahtteils in einer integrierten elektronischen schaltung |
Country Status (6)
Country | Link |
---|---|
US (1) | US7960255B2 (de) |
EP (1) | EP2229690B1 (de) |
JP (1) | JP2010541229A (de) |
AT (1) | ATE506696T1 (de) |
DE (1) | DE602008006465D1 (de) |
WO (1) | WO2009040328A1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8680510B2 (en) * | 2010-06-28 | 2014-03-25 | International Business Machines Corporation | Method of forming compound semiconductor |
GB201321949D0 (en) | 2013-12-12 | 2014-01-29 | Ibm | Semiconductor nanowire fabrication |
US9543440B2 (en) * | 2014-06-20 | 2017-01-10 | International Business Machines Corporation | High density vertical nanowire stack for field effect transistor |
US9449820B2 (en) * | 2014-12-22 | 2016-09-20 | International Business Machines Corporation | Epitaxial growth techniques for reducing nanowire dimension and pitch |
KR102537527B1 (ko) | 2018-09-10 | 2023-05-26 | 삼성전자 주식회사 | 집적회로 소자 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3854731B2 (ja) * | 1998-03-30 | 2006-12-06 | シャープ株式会社 | 微細構造の製造方法 |
US7163864B1 (en) * | 2000-10-18 | 2007-01-16 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US7078299B2 (en) * | 2003-09-03 | 2006-07-18 | Advanced Micro Devices, Inc. | Formation of finFET using a sidewall epitaxial layer |
KR100585157B1 (ko) | 2004-09-07 | 2006-05-30 | 삼성전자주식회사 | 다수의 와이어 브릿지 채널을 구비한 모스 트랜지스터 및그 제조방법 |
JP4367358B2 (ja) * | 2005-02-28 | 2009-11-18 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
-
2008
- 2008-09-22 DE DE602008006465T patent/DE602008006465D1/de active Active
- 2008-09-22 US US12/679,882 patent/US7960255B2/en not_active Expired - Fee Related
- 2008-09-22 EP EP08804548A patent/EP2229690B1/de not_active Not-in-force
- 2008-09-22 JP JP2010526260A patent/JP2010541229A/ja active Pending
- 2008-09-22 AT AT08804548T patent/ATE506696T1/de not_active IP Right Cessation
- 2008-09-22 WO PCT/EP2008/062622 patent/WO2009040328A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2009040328A1 (en) | 2009-04-02 |
US20100203712A1 (en) | 2010-08-12 |
JP2010541229A (ja) | 2010-12-24 |
EP2229690A1 (de) | 2010-09-22 |
EP2229690B1 (de) | 2011-04-20 |
US7960255B2 (en) | 2011-06-14 |
ATE506696T1 (de) | 2011-05-15 |
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