DE602006019433D1 - Technik zum bilden von kontaktisolationsschicht-silizidregionen mit verschiedenen eigenschaften - Google Patents

Technik zum bilden von kontaktisolationsschicht-silizidregionen mit verschiedenen eigenschaften

Info

Publication number
DE602006019433D1
DE602006019433D1 DE602006019433T DE602006019433T DE602006019433D1 DE 602006019433 D1 DE602006019433 D1 DE 602006019433D1 DE 602006019433 T DE602006019433 T DE 602006019433T DE 602006019433 T DE602006019433 T DE 602006019433T DE 602006019433 D1 DE602006019433 D1 DE 602006019433D1
Authority
DE
Germany
Prior art keywords
technique
insulation layer
different properties
forming contact
silicide regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006019433T
Other languages
English (en)
Inventor
Matthias Lehr
Kai Frohberg
Christoph Schwan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority claimed from PCT/US2006/019720 external-priority patent/WO2007005136A1/en
Publication of DE602006019433D1 publication Critical patent/DE602006019433D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE602006019433T 2005-06-30 2006-05-23 Technik zum bilden von kontaktisolationsschicht-silizidregionen mit verschiedenen eigenschaften Active DE602006019433D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102005030583A DE102005030583B4 (de) 2005-06-30 2005-06-30 Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement
US11/379,606 US7838359B2 (en) 2005-06-30 2006-04-21 Technique for forming contact insulation layers and silicide regions with different characteristics
PCT/US2006/019720 WO2007005136A1 (en) 2005-06-30 2006-05-23 Technique for forming contact insulation layers silicide regions with different characteristics

Publications (1)

Publication Number Publication Date
DE602006019433D1 true DE602006019433D1 (de) 2011-02-17

Family

ID=37545024

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102005030583A Active DE102005030583B4 (de) 2005-06-30 2005-06-30 Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement
DE602006019433T Active DE602006019433D1 (de) 2005-06-30 2006-05-23 Technik zum bilden von kontaktisolationsschicht-silizidregionen mit verschiedenen eigenschaften

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE102005030583A Active DE102005030583B4 (de) 2005-06-30 2005-06-30 Verfahren zur Herstellung von Kontaktisolationsschichten und Silizidgebieten mit unterschiedlichen Eigenschaften eines Halbleiterbauelements und Halbleiterbauelement

Country Status (5)

Country Link
US (1) US7838359B2 (de)
JP (1) JP4937253B2 (de)
CN (1) CN101213654B (de)
DE (2) DE102005030583B4 (de)
TW (1) TWI417992B (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200629454A (en) * 2005-02-14 2006-08-16 Powerchip Semiconductor Corp Method of detecting piping defect
US7858458B2 (en) * 2005-06-14 2010-12-28 Micron Technology, Inc. CMOS fabrication
DE102005041225B3 (de) * 2005-08-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung vertiefter verformter Drain/Source-Gebiete in NMOS- und PMOS-Transistoren
JP4880958B2 (ja) * 2005-09-16 2012-02-22 株式会社東芝 半導体装置及びその製造方法
US8039284B2 (en) * 2006-12-18 2011-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dual metal silicides for lowering contact resistance
DE102007004862B4 (de) 2007-01-31 2014-01-30 Globalfoundries Inc. Verfahren zur Herstellung von Si-Ge enthaltenden Drain/Source-Gebieten in Transistoren mit geringerem Si/Ge-Verlust
DE102007009916B4 (de) * 2007-02-28 2012-02-23 Advanced Micro Devices, Inc. Verfahren zum Entfernen unterschiedlicher Abstandshalter durch einen nasschemischen Ätzprozess
US20080290420A1 (en) * 2007-05-25 2008-11-27 Ming-Hua Yu SiGe or SiC layer on STI sidewalls
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7834389B2 (en) * 2007-06-15 2010-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Triangular space element for semiconductor device
TW200910526A (en) * 2007-07-03 2009-03-01 Renesas Tech Corp Method of manufacturing semiconductor device
DE102007041210B4 (de) * 2007-08-31 2012-02-02 Advanced Micro Devices, Inc. Verfahren zur Verspannungsübertragung in einem Zwischenschichtdielektrikum durch Vorsehen einer verspannten dielektrischen Schicht über einem verspannungsneutralen dielektrischen Material in einem Halbleiterbauelement und entsprechendes Halbleiterbauelement
US8058123B2 (en) * 2007-11-29 2011-11-15 Globalfoundries Singapore Pte. Ltd. Integrated circuit and method of fabrication thereof
DE102008011928B4 (de) * 2008-02-29 2010-06-02 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Halbleiterbauelements unter Verwendung einer Ätzstoppschicht mit geringerer Dicke zum Strukturieren eines dielektrischen Materials
DE102008054075B4 (de) * 2008-10-31 2010-09-23 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Abgesenktem Drain- und Sourcebereich in Verbindung mit einem Verfahren zur komplexen Silizidherstellung in Transistoren
KR101536562B1 (ko) * 2009-02-09 2015-07-14 삼성전자 주식회사 반도체 집적 회로 장치
JP5668277B2 (ja) 2009-06-12 2015-02-12 ソニー株式会社 半導体装置
US8487354B2 (en) * 2009-08-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving selectivity of epi process
CN102201369B (zh) * 2010-03-22 2014-03-19 中芯国际集成电路制造(上海)有限公司 一种制作具有应力层的互补金属氧化物半导体器件的方法
US20120080725A1 (en) * 2010-09-30 2012-04-05 Seagate Technology Llc Vertical transistor memory array
DE102010063298B4 (de) * 2010-12-16 2012-08-16 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Strukturierung eines verspannten dielektrischen Materials in einer Kontaktebene ohne Verwendung einer verbleibenden Ätzstoppschicht
US8987104B2 (en) * 2011-05-16 2015-03-24 Globalfoundries Inc. Method of forming spacers that provide enhanced protection for gate electrode structures
US9087903B2 (en) 2013-04-26 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer omega gate
US9177810B2 (en) 2014-01-29 2015-11-03 International Business Machines Corporation Dual silicide regions and method for forming the same
US9165838B2 (en) * 2014-02-26 2015-10-20 Taiwan Semiconductor Manufacturing Company Limited Methods of forming low resistance contacts
JP6297860B2 (ja) 2014-02-28 2018-03-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR102236555B1 (ko) 2014-11-11 2021-04-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102282980B1 (ko) 2015-01-05 2021-07-29 삼성전자주식회사 실리사이드를 갖는 반도체 소자 및 그 형성 방법
TWI672797B (zh) * 2015-08-26 2019-09-21 聯華電子股份有限公司 半導體結構及其製造方法
US10096523B2 (en) 2015-11-30 2018-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer structure and manufacturing method thereof
US9748281B1 (en) * 2016-09-15 2017-08-29 International Business Machines Corporation Integrated gate driver
JP6783703B2 (ja) * 2017-05-29 2020-11-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE102020101906A1 (de) * 2020-01-27 2021-07-29 Röchling Automotive SE & Co. KG Kanalbauteil für ein Kraftfahrzeug mit bedarfsgerecht dimensionierten integrierten elektrischen Leitungen
CN113314536A (zh) * 2020-02-27 2021-08-27 台湾积体电路制造股份有限公司 半导体器件和制造半导体器件的方法
US11508738B2 (en) * 2020-02-27 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM speed and margin optimization via spacer tuning

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142004A (en) * 1976-01-22 1979-02-27 Bell Telephone Laboratories, Incorporated Method of coating semiconductor substrates
JPH07235606A (ja) * 1994-02-22 1995-09-05 Mitsubishi Electric Corp 相補型半導体装置及びその製造方法
US5882973A (en) 1997-01-27 1999-03-16 Advanced Micro Devices, Inc. Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles
US6391750B1 (en) 1999-08-18 2002-05-21 Advanced Micro Devices, Inc. Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness
JP4597479B2 (ja) * 2000-11-22 2010-12-15 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2003086708A (ja) 2000-12-08 2003-03-20 Hitachi Ltd 半導体装置及びその製造方法
JP4865152B2 (ja) * 2001-06-19 2012-02-01 セイコーインスツル株式会社 半導体装置の製造方法
DE10208904B4 (de) * 2002-02-28 2007-03-01 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung unterschiedlicher Silicidbereiche auf verschiedenen Silicium enthaltenden Gebieten in einem Halbleiterelement
JP2005519468A (ja) 2002-02-28 2005-06-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 半導体デバイス中の異なるシリコン含有領域上に、異なるシリサイド部分を形成する方法
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6806584B2 (en) * 2002-10-21 2004-10-19 International Business Machines Corporation Semiconductor device structure including multiple fets having different spacer widths
US7022561B2 (en) 2002-12-02 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device
US6825529B2 (en) 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US7112483B2 (en) * 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types
US6906360B2 (en) * 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US6869866B1 (en) * 2003-09-22 2005-03-22 International Business Machines Corporation Silicide proximity structures for CMOS device performance improvements
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US8008724B2 (en) 2003-10-30 2011-08-30 International Business Machines Corporation Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
JP2007528123A (ja) * 2003-10-31 2007-10-04 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 高さが異なる隆起したドレインおよびソース領域を有するトランジスタを形成するための先進技術
US7176522B2 (en) 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
US7064396B2 (en) * 2004-03-01 2006-06-20 Freescale Semiconductor, Inc. Integrated circuit with multiple spacer insulating region widths
US20060024879A1 (en) * 2004-07-31 2006-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Selectively strained MOSFETs to improve drive current
US20060163670A1 (en) * 2005-01-27 2006-07-27 International Business Machines Corporation Dual silicide process to improve device performance

Also Published As

Publication number Publication date
JP2009500823A (ja) 2009-01-08
TWI417992B (zh) 2013-12-01
DE102005030583B4 (de) 2010-09-30
US20070001233A1 (en) 2007-01-04
CN101213654A (zh) 2008-07-02
US7838359B2 (en) 2010-11-23
DE102005030583A1 (de) 2007-01-04
JP4937253B2 (ja) 2012-05-23
TW200709342A (en) 2007-03-01
CN101213654B (zh) 2011-09-28

Similar Documents

Publication Publication Date Title
DE602006019433D1 (de) Technik zum bilden von kontaktisolationsschicht-silizidregionen mit verschiedenen eigenschaften
DE602007009162D1 (de) Array-Substrat mit Kupferleitern und Herstellungsverfahren dafür
DE602006004024D1 (de) Handschuhe mit erhöhter stulpenrutschfester oberfläche
EP2175504A4 (de) Organisches elektrolumineszenzelement und verfahren zu seiner herstellung
DE602005005007D1 (de) FET-Biosensor mit Oberflächenänderung
EP2178343A4 (de) Lichtdurchlässiges substrat, verfahren zur herstellung des lichtdurchlässigen substrats, organische leuchtdiode und verfahren zur herstellung der organischen leuchtdiode
FR2917996B1 (fr) Pneumatique avec une couche auto-obturante.
DE602006011634D1 (de) Konstruktion mit verbindungsschicht
GB0506899D0 (en) Multiple conductive layer TFT
DK2054896T3 (da) Dielektrisk materiale med ledende eller halvledende organisk materiale
DE602007009238D1 (de) Biplanare elektrode mit sperr-gates
EP1794359A4 (de) Doppellagiges formiergewebe mit hoher undurchlässigkeit in der mittelebene
DE602006008312D1 (de) Mesostrukturiertes material mit hohem aluminiumgehalt
DE602005000143D1 (de) Stellantrieb mit kammförmiger Elektrode
EP2111642A4 (de) Organischer transistor und herstellungsverfahren dafür
GB201003881D0 (en) MOS structures that exhibit lower contact resistance and methods for fabricating the same
EP2154688A4 (de) Elektrisches kontaktmaterial, verfahren zur herstellung des elektrischen kontaktmaterials und elektrischer kontakt
TWI370485B (en) Semiconductor device fabrication method, semiconductor device, and semiconductor layer formation method
DE502005006280D1 (de) Elektrisch ansteuerbares ventil
DE602006001975D1 (de) Kartonformeinrichtung mit schwenkbaren Vorrichtungen mit Rollen
EP2123658A4 (de) Material zur bildung eines siliziumhaltigen films, und siliziumhaltige isolierfilm und verfahren zu dessen bildung
DE502005008755D1 (de) Elektrisch ansteuerbares ventil
EP2068379A4 (de) Organisches halbleitermaterial, organisches halbleiterbauelement damit und herstellungsverfahren dafür
EP2117009A4 (de) Organisches isolierendes material, lack für eine organische isolierende folie damit, organische isolierende folie und halbleitervorrichtung
EP2224472A4 (de) Substrat und verfahren zu seiner herstellung