DE602006006600D1 - Verfahren und vorrichtung zum aufzeichnen von hochgeschwindigkeitseingangsdaten in einer matrix von speicheranordnungen - Google Patents

Verfahren und vorrichtung zum aufzeichnen von hochgeschwindigkeitseingangsdaten in einer matrix von speicheranordnungen

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Publication number
DE602006006600D1
DE602006006600D1 DE602006006600T DE602006006600T DE602006006600D1 DE 602006006600 D1 DE602006006600 D1 DE 602006006600D1 DE 602006006600 T DE602006006600 T DE 602006006600T DE 602006006600 T DE602006006600 T DE 602006006600T DE 602006006600 D1 DE602006006600 D1 DE 602006006600D1
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DE
Germany
Prior art keywords
flash
matrix
current
devices
page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006006600T
Other languages
English (en)
Inventor
Thomas Brune
Jens Peter Wittenburg
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of DE602006006600D1 publication Critical patent/DE602006006600D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
DE602006006600T 2006-01-16 2006-12-04 Verfahren und vorrichtung zum aufzeichnen von hochgeschwindigkeitseingangsdaten in einer matrix von speicheranordnungen Active DE602006006600D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06090010A EP1808863A1 (de) 2006-01-16 2006-01-16 Verfahren und Vorrichtung zur Aufzeichnung von Hochgeschwindigkeitseingabedaten auf einer Speichergerätematrix
PCT/EP2006/069265 WO2007080031A1 (en) 2006-01-16 2006-12-04 Method and apparatus for recording high-speed input data into a matrix of memory devices

Publications (1)

Publication Number Publication Date
DE602006006600D1 true DE602006006600D1 (de) 2009-06-10

Family

ID=36763177

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006006600T Active DE602006006600D1 (de) 2006-01-16 2006-12-04 Verfahren und vorrichtung zum aufzeichnen von hochgeschwindigkeitseingangsdaten in einer matrix von speicheranordnungen

Country Status (12)

Country Link
US (1) US7802152B2 (de)
EP (2) EP1808863A1 (de)
JP (1) JP5160448B2 (de)
KR (1) KR101261671B1 (de)
CN (1) CN101361137B (de)
AT (1) ATE430364T1 (de)
AU (1) AU2006334660B2 (de)
CA (1) CA2636237C (de)
DE (1) DE602006006600D1 (de)
RU (1) RU2417461C2 (de)
TW (1) TWI403896B (de)
WO (1) WO2007080031A1 (de)

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* Cited by examiner, † Cited by third party
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CN101715145B (zh) 2008-10-06 2012-08-15 辉达公司 利用级联存储器评估处理能力的设备和方法
US7945822B1 (en) * 2009-04-27 2011-05-17 Netapp, Inc. Storing data to multi-chip low-latency random read memory device using non-aligned striping
EP2270662A1 (de) * 2009-06-29 2011-01-05 Thomson Licensing Verfahren und Vorrichtung zur Behandlung von Schreibfehlern beim Schreiben von Informationsdaten ein Flash-Speichervorrichtungen
EP2388706A1 (de) * 2010-05-21 2011-11-23 Thomson Licensing Verfahren und System für Echtzeit-Streaming und -Speicherung
KR102072449B1 (ko) 2012-06-01 2020-02-04 삼성전자주식회사 불휘발성 메모리 장치를 포함하는 저장 장치 및 그것의 리페어 방법
US9026893B1 (en) * 2012-12-13 2015-05-05 Western Digital Technologies, Inc. Dynamically assigning inactive pages not used in Reed-Solomon code in non-volatile solid-state storage array
US9502139B1 (en) 2012-12-18 2016-11-22 Intel Corporation Fine grained online remapping to handle memory errors
US9286176B1 (en) 2013-11-08 2016-03-15 Western Digital Technologies, Inc. Selective skipping of blocks in an SSD
US10120816B2 (en) * 2016-07-20 2018-11-06 Sandisk Technologies Llc Bad column management with data shuffle in pipeline
CN107423159B (zh) * 2017-07-11 2019-06-28 华中科技大学 一种基于闪存错误模式提升ldpc译码性能的方法
CN107395214B (zh) * 2017-07-12 2019-06-28 华中科技大学 一种基于闪存页错误特性降低ldpc译码延迟的方法
CN107391299B (zh) * 2017-07-17 2019-06-18 华中科技大学 一种提升闪存存储系统读性能的方法
US11475102B2 (en) * 2019-02-21 2022-10-18 Samsung Electronics Co., Ltd. Adaptive matrix multiplication accelerator for machine learning and deep learning applications

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US6347051B2 (en) * 1991-11-26 2002-02-12 Hitachi, Ltd. Storage device employing a flash memory
JP3267320B2 (ja) * 1992-03-31 2002-03-18 株式会社東芝 不揮発性半導体メモリ装置及び不揮発性半導体メモリ装置の制御方法
JP3215237B2 (ja) * 1993-10-01 2001-10-02 富士通株式会社 記憶装置および記憶装置の書き込み／消去方法
JP3154892B2 (ja) * 1994-05-10 2001-04-09 株式会社東芝 Ｉｃメモリカードおよびそのｉｃメモリカードの検査方法
US5708771A (en) * 1995-11-21 1998-01-13 Emc Corporation Fault tolerant controller system and method
KR100389867B1 (ko) * 2001-06-04 2003-07-04 삼성전자주식회사 플래시 메모리 관리방법
US7168010B2 (en) * 2002-08-12 2007-01-23 Intel Corporation Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations
KR100532413B1 (ko) * 2002-12-02 2005-12-02 삼성전자주식회사 플래시 메모리 보호 장치 및 방법
US20040153902A1 (en) * 2003-01-21 2004-08-05 Nexflash Technologies, Inc. Serial flash integrated circuit having error detection and correction
KR100543447B1 (ko) * 2003-04-03 2006-01-23 삼성전자주식회사 에러정정기능을 가진 플래쉬메모리장치
US7392436B2 (en) * 2003-05-08 2008-06-24 Micron Technology, Inc. Program failure recovery
US7606993B2 (en) * 2003-06-10 2009-10-20 Tdk Corporation Flash memory controller, memory control circuit, flash memory system, and method for controlling data exchange between host computer and flash memory
JP4595342B2 (ja) * 2004-02-19 2010-12-08 日本電気株式会社 記憶装置のデータ書き込み、読み出し方法およびデータ記憶システム
JP4722839B2 (ja) * 2004-05-19 2011-07-13 パナソニック株式会社 メモリ制御回路、不揮発性記憶装置及びメモリ制御方法
KR100845526B1 (ko) * 2006-10-19 2008-07-10 삼성전자주식회사 플래시 메모리를 포함한 메모리 시스템 및 그것의 프로그램방법

Also Published As

Publication number Publication date
TW200739341A (en) 2007-10-16
AU2006334660A1 (en) 2007-07-19
JP2009524127A (ja) 2009-06-25
EP1974354A1 (de) 2008-10-01
RU2417461C2 (ru) 2011-04-27
ATE430364T1 (de) 2009-05-15
JP5160448B2 (ja) 2013-03-13
TWI403896B (zh) 2013-08-01
CA2636237C (en) 2014-07-08
CA2636237A1 (en) 2007-07-19
KR20080092364A (ko) 2008-10-15
US20090083591A1 (en) 2009-03-26
CN101361137A (zh) 2009-02-04
CN101361137B (zh) 2011-06-22
EP1808863A1 (de) 2007-07-18
AU2006334660B2 (en) 2011-08-25
RU2008133604A (ru) 2010-02-27
WO2007080031A1 (en) 2007-07-19
KR101261671B1 (ko) 2013-05-06
US7802152B2 (en) 2010-09-21
EP1974354B1 (de) 2009-04-29

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8364 No opposition during term of opposition