DE602005015746D1 - Verfahren zur Herstellung einer relaxierten SiGe-Schicht - Google Patents
Verfahren zur Herstellung einer relaxierten SiGe-SchichtInfo
- Publication number
- DE602005015746D1 DE602005015746D1 DE602005015746T DE602005015746T DE602005015746D1 DE 602005015746 D1 DE602005015746 D1 DE 602005015746D1 DE 602005015746 T DE602005015746 T DE 602005015746T DE 602005015746 T DE602005015746 T DE 602005015746T DE 602005015746 D1 DE602005015746 D1 DE 602005015746D1
- Authority
- DE
- Germany
- Prior art keywords
- buffer layer
- layer
- producing
- sige layer
- sige buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910000577 Silicon-germanium Inorganic materials 0.000 title abstract 7
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 239000007943 implant Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB0424290.5A GB0424290D0 (en) | 2004-11-02 | 2004-11-02 | Method of growing a strained layer |
| PCT/IB2005/053523 WO2006048800A1 (en) | 2004-11-02 | 2005-10-28 | Method of growing a strained layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602005015746D1 true DE602005015746D1 (de) | 2009-09-10 |
Family
ID=33515953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602005015746T Active DE602005015746D1 (de) | 2004-11-02 | 2005-10-28 | Verfahren zur Herstellung einer relaxierten SiGe-Schicht |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US7785993B2 (de) |
| EP (1) | EP1810320B1 (de) |
| JP (1) | JP2008519428A (de) |
| KR (1) | KR20070074591A (de) |
| CN (1) | CN100492590C (de) |
| AT (1) | ATE438196T1 (de) |
| DE (1) | DE602005015746D1 (de) |
| GB (1) | GB0424290D0 (de) |
| TW (1) | TW200623239A (de) |
| WO (1) | WO2006048800A1 (de) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8692310B2 (en) | 2009-02-09 | 2014-04-08 | Spansion Llc | Gate fringing effect based channel formation for semiconductor device |
| CN102427068B (zh) * | 2011-12-02 | 2014-06-18 | 中国科学院上海微系统与信息技术研究所 | 单片集成具有晶格失配的晶体模板及其制作方法 |
| CN103165420B (zh) * | 2011-12-14 | 2015-11-18 | 中国科学院上海微系统与信息技术研究所 | 一种SiGe中嵌入超晶格制备应变Si的方法 |
| CN103632930B (zh) * | 2012-08-28 | 2016-06-15 | 中国科学院上海微系统与信息技术研究所 | 利用超薄层吸附制备绝缘体上超薄改性材料的方法 |
| KR102130056B1 (ko) | 2013-11-15 | 2020-07-03 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법 |
| EP3573094B1 (de) * | 2014-11-18 | 2023-01-04 | GlobalWafers Co., Ltd. | Hochresistiver halbleiter-auf-isolator-wafer und verfahren zur herstellung |
| US9570298B1 (en) | 2015-12-09 | 2017-02-14 | International Business Machines Corporation | Localized elastic strain relaxed buffer |
| JP6493197B2 (ja) * | 2015-12-18 | 2019-04-03 | 株式会社Sumco | シリコンゲルマニウムエピタキシャルウェーハの製造方法およびシリコンゲルマニウムエピタキシャルウェーハ |
| US9831324B1 (en) * | 2016-08-12 | 2017-11-28 | International Business Machines Corporation | Self-aligned inner-spacer replacement process using implantation |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US87119A (en) * | 1869-02-23 | Improved tanners leach | ||
| US115888A (en) * | 1871-06-13 | John pfeifeb | ||
| JPS5768015A (en) * | 1980-10-16 | 1982-04-26 | Toshiba Corp | Manufacture of semiconductor device |
| GB8522833D0 (en) * | 1985-09-16 | 1985-10-23 | Exxon Chemical Patents Inc | Dithiophosphonates |
| US6746902B2 (en) | 2002-01-31 | 2004-06-08 | Sharp Laboratories Of America, Inc. | Method to form relaxed sige layer with high ge content |
| US6703293B2 (en) * | 2002-07-11 | 2004-03-09 | Sharp Laboratories Of America, Inc. | Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates |
| US6858506B2 (en) | 2002-08-08 | 2005-02-22 | Macronix International Co., Ltd. | Method for fabricating locally strained channel |
| JP2004103805A (ja) * | 2002-09-09 | 2004-04-02 | Sharp Corp | 半導体基板の製造方法、半導体基板及び半導体装置 |
| US6825102B1 (en) * | 2003-09-18 | 2004-11-30 | International Business Machines Corporation | Method of improving the quality of defective semiconductor material |
| US6872641B1 (en) * | 2003-09-23 | 2005-03-29 | International Business Machines Corporation | Strained silicon on relaxed sige film with uniform misfit dislocation density |
-
2004
- 2004-11-02 GB GBGB0424290.5A patent/GB0424290D0/en not_active Ceased
-
2005
- 2005-10-28 TW TW094137989A patent/TW200623239A/zh unknown
- 2005-10-28 US US11/718,488 patent/US7785993B2/en active Active
- 2005-10-28 WO PCT/IB2005/053523 patent/WO2006048800A1/en active Application Filing
- 2005-10-28 JP JP2007538591A patent/JP2008519428A/ja not_active Withdrawn
- 2005-10-28 AT AT05797345T patent/ATE438196T1/de not_active IP Right Cessation
- 2005-10-28 DE DE602005015746T patent/DE602005015746D1/de active Active
- 2005-10-28 KR KR1020077009893A patent/KR20070074591A/ko not_active Application Discontinuation
- 2005-10-28 CN CNB2005800374973A patent/CN100492590C/zh active Active
- 2005-10-28 EP EP05797345A patent/EP1810320B1/de active Active
Also Published As
| Publication number | Publication date |
|---|---|
| WO2006048800A1 (en) | 2006-05-11 |
| EP1810320A1 (de) | 2007-07-25 |
| GB0424290D0 (en) | 2004-12-01 |
| US20090042374A1 (en) | 2009-02-12 |
| EP1810320B1 (de) | 2009-07-29 |
| CN101053064A (zh) | 2007-10-10 |
| KR20070074591A (ko) | 2007-07-12 |
| ATE438196T1 (de) | 2009-08-15 |
| JP2008519428A (ja) | 2008-06-05 |
| TW200623239A (en) | 2006-07-01 |
| CN100492590C (zh) | 2009-05-27 |
| US7785993B2 (en) | 2010-08-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |