DE602005005084D1 - Testfähige integrierte schaltung - Google Patents

Testfähige integrierte schaltung

Info

Publication number
DE602005005084D1
DE602005005084D1 DE602005005084T DE602005005084T DE602005005084D1 DE 602005005084 D1 DE602005005084 D1 DE 602005005084D1 DE 602005005084 T DE602005005084 T DE 602005005084T DE 602005005084 T DE602005005084 T DE 602005005084T DE 602005005084 D1 DE602005005084 D1 DE 602005005084D1
Authority
DE
Germany
Prior art keywords
circuit
integrated circuit
time interval
test time
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005005084T
Other languages
English (en)
Other versions
DE602005005084T2 (de
Inventor
Cuyper Steven H De
Graeme Francis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE602005005084D1 publication Critical patent/DE602005005084D1/de
Application granted granted Critical
Publication of DE602005005084T2 publication Critical patent/DE602005005084T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602005005084T 2004-11-10 2005-10-28 Testfähige integrierte schaltung Active DE602005005084T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0424766 2004-11-10
GB0424766A GB0424766D0 (en) 2004-11-10 2004-11-10 Testable integrated circuit
PCT/IB2005/053527 WO2006051438A1 (en) 2004-11-10 2005-10-28 Testable integrated circuit

Publications (2)

Publication Number Publication Date
DE602005005084D1 true DE602005005084D1 (de) 2008-04-10
DE602005005084T2 DE602005005084T2 (de) 2009-03-19

Family

ID=33523442

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005005084T Active DE602005005084T2 (de) 2004-11-10 2005-10-28 Testfähige integrierte schaltung

Country Status (9)

Country Link
US (1) US7482827B2 (de)
EP (1) EP1812803B1 (de)
JP (1) JP2008519974A (de)
KR (1) KR20070085923A (de)
CN (1) CN101052887B (de)
AT (1) ATE387632T1 (de)
DE (1) DE602005005084T2 (de)
GB (1) GB0424766D0 (de)
WO (1) WO2006051438A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7750618B1 (en) * 2006-07-25 2010-07-06 Integrated Device Technology, Inc. System and method for testing a clock circuit
US11821946B2 (en) 2021-09-15 2023-11-21 Nxp Usa, Inc. Built in self test (BIST) for clock generation circuitry

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05259848A (ja) * 1992-03-11 1993-10-08 Nec Corp クロック発生装置
GB9417244D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Integrated circuit device and test method therefor
WO1998026301A1 (en) * 1996-12-13 1998-06-18 Koninklijke Philips Electronics N.V. Integrated circuit comprising a first and a second clock domain and a method for testing such a circuit
JP2853696B2 (ja) * 1997-02-26 1999-02-03 日本電気株式会社 Ｓｒｔｓ受信装置
MXPA02008946A (es) * 2000-03-24 2003-02-10 Thomson Licensing Sa Aparato oscilador que se puede probar y controlar para un circuito integrado.
DE60122960T2 (de) * 2000-04-20 2007-03-29 Texas Instruments Incorporated, Dallas Digitale eingebaute Selbsttestschaltungsanordnung für Phasenregelschleife
US6954887B2 (en) * 2001-03-22 2005-10-11 Syntest Technologies, Inc. Multiple-capture DFT system for scan-based integrated circuits
US7065684B1 (en) * 2002-04-18 2006-06-20 Xilinx, Inc. Circuits and methods for measuring signal propagation delays on integrated circuits

Also Published As

Publication number Publication date
WO2006051438A1 (en) 2006-05-18
KR20070085923A (ko) 2007-08-27
EP1812803A1 (de) 2007-08-01
ATE387632T1 (de) 2008-03-15
US7482827B2 (en) 2009-01-27
EP1812803B1 (de) 2008-02-27
CN101052887B (zh) 2010-05-12
DE602005005084T2 (de) 2009-03-19
CN101052887A (zh) 2007-10-10
JP2008519974A (ja) 2008-06-12
GB0424766D0 (en) 2004-12-08
US20080204063A1 (en) 2008-08-28

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Legal Events

Date Code Title Description
8381 Inventor (new situation)

Inventor name: DE CUYPER, STEVEN H., REDHILL, SURREY RH1 5HA, GB

Inventor name: FRANCIS, GRAEME, REDHILL, SURREY RH1 5HA, GB

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL