ATE492818T1 - Ic-testverfahren und vorrichtungen - Google Patents

Ic-testverfahren und vorrichtungen

Info

Publication number
ATE492818T1
ATE492818T1 AT07700042T AT07700042T ATE492818T1 AT E492818 T1 ATE492818 T1 AT E492818T1 AT 07700042 T AT07700042 T AT 07700042T AT 07700042 T AT07700042 T AT 07700042T AT E492818 T1 ATE492818 T1 AT E492818T1
Authority
AT
Austria
Prior art keywords
test
clock
clocked
clk
integrated circuit
Prior art date
Application number
AT07700042T
Other languages
English (en)
Inventor
Tom Waayers
Johan Meirlevede
David Price
Norbert Schomann
Ruediger Solbach
Herve Fleury
Jozef Poels
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE492818T1 publication Critical patent/ATE492818T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
AT07700042T 2006-01-06 2007-01-04 Ic-testverfahren und vorrichtungen ATE492818T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06100139 2006-01-06
PCT/IB2007/050025 WO2007077542A2 (en) 2006-01-06 2007-01-04 Ic testing methods and apparatus

Publications (1)

Publication Number Publication Date
ATE492818T1 true ATE492818T1 (de) 2011-01-15

Family

ID=38228595

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07700042T ATE492818T1 (de) 2006-01-06 2007-01-04 Ic-testverfahren und vorrichtungen

Country Status (8)

Country Link
US (1) US8327205B2 (de)
EP (1) EP1982205B1 (de)
JP (1) JP2009522571A (de)
CN (1) CN101371153B (de)
AT (1) ATE492818T1 (de)
DE (1) DE602007011397D1 (de)
TW (1) TW200801550A (de)
WO (1) WO2007077542A2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5029161B2 (ja) * 2007-06-15 2012-09-19 株式会社デンソー 半導体集積装置
KR101213166B1 (ko) * 2008-09-17 2012-12-18 가부시키가이샤 어드밴티스트 시험 장치 및 도메인간 동기 방법
TW201140308A (en) * 2010-03-15 2011-11-16 Kyushu Inst Technology Semiconductor device, detection method, and program
US8788895B2 (en) * 2010-04-08 2014-07-22 Stmicroelectronics S.R.L. Testing system for integrated circuits including components for receiving clock signals corresponding to different clock domains
US8578226B2 (en) * 2010-08-17 2013-11-05 Eigenix Apparatus and system for implementing variable speed scan testing
US9021323B1 (en) * 2011-03-11 2015-04-28 Altera Corporation Test techniques and circuitry
US8856602B2 (en) * 2011-12-20 2014-10-07 International Business Machines Corporation Multi-core processor with internal voting-based built in self test (BIST)
CN102928766B (zh) * 2012-10-26 2015-01-21 福州瑞芯微电子有限公司 一种在芯片高速测试中配置参数的方法
US9052075B2 (en) * 2013-03-15 2015-06-09 Cree, Inc. Standardized troffer fixture
US9086457B2 (en) 2013-03-26 2015-07-21 International Business Machines Corporation Scan chain latch design that improves testability of integrated circuits
US9377511B2 (en) * 2013-11-19 2016-06-28 Infineon Technologies Ag Coverage enhancement and power aware clock system for structural delay-fault test
US9234938B2 (en) * 2014-05-06 2016-01-12 Stmicroelectronics International N.V. Monitoring on-chip clock control during integrated circuit testing
US9515686B2 (en) 2014-08-11 2016-12-06 Samsung Electronics Co., Ltd. Signal transmitting circuit using common clock, and storage device therewith
US9666301B2 (en) 2014-09-16 2017-05-30 Qualcomm Incorporated Scannable memories with robust clocking methodology to prevent inadvertent reads or writes
TWI629493B (zh) * 2014-10-29 2018-07-11 南韓商因諾帝歐股份有限公司 積體電路晶片測試裝置，方法及系統
JP6498031B2 (ja) * 2015-05-18 2019-04-10 セイコーインスツル株式会社 分周回路、分周回路の制御方法およびアナログ電子時計
TWI603104B (zh) * 2015-09-14 2017-10-21 Integrated circuit with scan test and test method
US9892024B2 (en) * 2015-11-02 2018-02-13 Sony Interactive Entertainment America Llc Backward compatibility testing of software in a mode that disrupts timing
KR102468792B1 (ko) * 2015-11-13 2022-11-18 삼성전자주식회사 인터페이스 보드, 그를 포함하는 mcp 테스트 시스템 및 이를 이용한 mcp 테스트 방법
KR102355437B1 (ko) * 2017-05-11 2022-01-26 에스케이하이닉스 주식회사 클럭 생성 회로를 포함하는 반도체 장치 및 반도체 시스템
US11087857B2 (en) * 2017-11-15 2021-08-10 Texas Instruments Incorporated Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths
US10459029B2 (en) 2018-01-08 2019-10-29 Seagate Technology Llc On-chip clock control monitoring
US10628275B2 (en) * 2018-03-07 2020-04-21 Nxp B.V. Runtime software-based self-test with mutual inter-core checking
CN109828551A (zh) * 2019-02-18 2019-05-31 深圳高新兴物联科技有限公司 自动化测试方法、装置以及计算机可读存储介质
CN109839586A (zh) * 2019-03-11 2019-06-04 世芯电子科技(无锡)有限公司 一种soc芯片ip时钟在dft中的处理技术
US11353496B2 (en) * 2019-05-08 2022-06-07 Hamilton Sundstrand Corporation Frequency-based built-in-test for discrete outputs
CN112924850A (zh) * 2021-01-27 2021-06-08 胜达克半导体科技(上海)有限公司 一种应用于自动测试机soc芯片并行测试切换方法
CN113190394B (zh) * 2021-07-02 2021-09-28 南京宏泰半导体科技有限公司 一种面向soc芯片的多时钟域并发测试系统及其测试方法
US20230384378A1 (en) * 2022-05-31 2023-11-30 Renesas Electronics Corporation Semiconductor device and scan testing method
CN117890753A (zh) * 2022-10-08 2024-04-16 深圳市中兴微电子技术有限公司 芯片测试方法、寄存器、电子设备和存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW307927B (de) * 1994-08-29 1997-06-11 Matsushita Electric Ind Co Ltd
US7590910B2 (en) * 1998-03-27 2009-09-15 Texas Instruments Incorporated Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports
US6418545B1 (en) * 1999-06-04 2002-07-09 Koninklijke Philips Electronics N.V. System and method to reduce scan test pins on an integrated circuit
GB0119300D0 (en) * 2001-08-08 2001-10-03 Koninkl Philips Electronics Nv Delay fault test circuitry and related method
US7444567B2 (en) * 2002-04-09 2008-10-28 Syntest Technologies, Inc. Method and apparatus for unifying self-test with scan-test during prototype debug and production test
US6671839B1 (en) * 2002-06-27 2003-12-30 Logicvision, Inc. Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith
US7103814B2 (en) * 2002-10-25 2006-09-05 International Business Machines Corporation Testing logic and embedded memory in parallel
US7373568B1 (en) * 2003-01-21 2008-05-13 Marvell Israel Ltd. Scan insertion
US7155651B2 (en) * 2004-04-22 2006-12-26 Logicvision, Inc. Clock controller for at-speed testing of scan circuits
US7380189B2 (en) * 2004-06-15 2008-05-27 Broadcom Corporation Circuit for PLL-based at-speed scan testing
US7721170B2 (en) * 2007-10-19 2010-05-18 International Business Machines Corporation Apparatus and method for selectively implementing launch off scan capability in at speed testing

Also Published As

Publication number Publication date
WO2007077542A3 (en) 2007-10-18
US20090003424A1 (en) 2009-01-01
EP1982205B1 (de) 2010-12-22
DE602007011397D1 (de) 2011-02-03
TW200801550A (en) 2008-01-01
JP2009522571A (ja) 2009-06-11
CN101371153B (zh) 2011-09-28
EP1982205A2 (de) 2008-10-22
WO2007077542A2 (en) 2007-07-12
US8327205B2 (en) 2012-12-04
CN101371153A (zh) 2009-02-18

Similar Documents

Publication Publication Date Title
ATE492818T1 (de) Ic-testverfahren und vorrichtungen
US7840863B2 (en) Functional frequency testing of integrated circuits
US8527824B2 (en) Testing of multi-clock domains
US7516379B2 (en) Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)
US9500706B2 (en) Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support
US8677201B2 (en) Semiconductor integrated circuit and method of retrieving signal to semiconductor integrated circuit
JP2007218808A (ja) 複数のクロック発生回路を含むテスト可能な集積回路
US7987401B2 (en) System and method for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing
EP4249928A1 (de) Schaltung und verfahren zur abtastprüfung
US20170328952A1 (en) Wide-Range Clock Signal Generation For Speed Grading Of Logic Cores
DE60206845D1 (de) Testsystem
US7380189B2 (en) Circuit for PLL-based at-speed scan testing
US7131041B2 (en) Semiconductor integrated circuit device and device for testing same
US20240012051A1 (en) Scan circuit and method
KR100907254B1 (ko) Ｉｅｅｅ 1500 래퍼를 갖는 시스템 온 칩 및 그것의 내부지연 테스트 방법
JP2006038743A (ja) 半導体集積回路装置及びその試験装置
US20100138709A1 (en) Method and apparatus for delay fault coverage enhancement
US6671841B1 (en) Method for on-line circuit debug using JTAG and shadow scan in a microprocessor
US6519724B1 (en) Communication systems, circuits, circuit systems and methods of operating a circuit
Furukawa et al. A novel and practical control scheme for inter-clock at-speed testing
US6662325B1 (en) Apparatus for on-line circuit debug using JTAG and shadow scan in a microprocessor
Cheon et al. At-speed logic BIST for IP cores
US11486928B2 (en) Electronic circuit and corresponding method of testing electronic circuits
US20170176535A1 (en) Clock gating for x-bounding timing exceptions in ic testing
Mozaffari et al. On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST)

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties