DE602004022045D1 - Test von ram adressdekodierern auf widerstandsbehaftete leiterunterbrechungen - Google Patents

Test von ram adressdekodierern auf widerstandsbehaftete leiterunterbrechungen

Info

Publication number
DE602004022045D1
DE602004022045D1 DE602004022045T DE602004022045T DE602004022045D1 DE 602004022045 D1 DE602004022045 D1 DE 602004022045D1 DE 602004022045 T DE602004022045 T DE 602004022045T DE 602004022045 T DE602004022045 T DE 602004022045T DE 602004022045 D1 DE602004022045 D1 DE 602004022045D1
Authority
DE
Germany
Prior art keywords
ram address
address decoders
resistive circuit
circuit breakdown
testing ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004022045T
Other languages
English (en)
Inventor
Mohamed Azimane
Ananta K Majhi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602004022045D1 publication Critical patent/DE602004022045D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
DE602004022045T 2003-05-22 2004-05-14 Test von ram adressdekodierern auf widerstandsbehaftete leiterunterbrechungen Expired - Lifetime DE602004022045D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03101471 2003-05-22
PCT/IB2004/050696 WO2004105043A1 (en) 2003-05-22 2004-05-14 Testing ram address decoder for resistive open defects

Publications (1)

Publication Number Publication Date
DE602004022045D1 true DE602004022045D1 (de) 2009-08-27

Family

ID=33462202

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004022045T Expired - Lifetime DE602004022045D1 (de) 2003-05-22 2004-05-14 Test von ram adressdekodierern auf widerstandsbehaftete leiterunterbrechungen

Country Status (8)

Country Link
US (1) US7392465B2 (de)
EP (1) EP1629505B1 (de)
JP (1) JP2007505439A (de)
KR (1) KR20060014057A (de)
CN (1) CN1791942B (de)
DE (1) DE602004022045D1 (de)
TW (1) TWI330717B (de)
WO (1) WO2004105043A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4608891B2 (ja) * 2004-01-30 2011-01-12 株式会社デンソー Ｒｏｍのデコーダテスト回路装置
US7916544B2 (en) * 2008-01-25 2011-03-29 Micron Technology, Inc. Random telegraph signal noise reduction scheme for semiconductor memories
US7808849B2 (en) * 2008-07-08 2010-10-05 Nvidia Corporation Read leveling of memory units designed to receive access requests in a sequential chained topology
US7796465B2 (en) * 2008-07-09 2010-09-14 Nvidia Corporation Write leveling of memory units designed to receive access requests in a sequential chained topology
US8461884B2 (en) * 2008-08-12 2013-06-11 Nvidia Corporation Programmable delay circuit providing for a wide span of delays
US8516315B2 (en) 2010-09-03 2013-08-20 Stmicroelectronics International N.V. Testing of non stuck-at faults in memory
US9122891B2 (en) * 2013-08-12 2015-09-01 Microsoft Technology Licensing, Llc Functional timing sensors
US11435940B2 (en) * 2021-02-02 2022-09-06 Nxp B.V. Testing a memory which includes conservative reversible logic

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891811A (en) * 1987-02-13 1990-01-02 International Business Machines Corporation Efficient address test for large memories
TW243531B (de) * 1993-09-03 1995-03-21 Motorola Inc
US5642362A (en) * 1994-07-20 1997-06-24 International Business Machines Corporation Scan-based delay tests having enhanced test vector pattern generation
EP0738418B1 (de) * 1994-11-09 2002-01-16 Koninklijke Philips Electronics N.V. Verfahren zum testen einer speicheradressen-dekodierschaltung
JPH10106286A (ja) * 1996-09-24 1998-04-24 Mitsubishi Electric Corp 半導体記憶装置およびそのテスト方法
DE19911939C2 (de) * 1999-03-17 2001-03-22 Siemens Ag Verfahren für den eingebauten Selbsttest einer elektronischen Schaltung
US6345373B1 (en) * 1999-03-29 2002-02-05 The University Of California System and method for testing high speed VLSI devices using slower testers
US6453437B1 (en) * 1999-07-01 2002-09-17 Synopsys, Inc. Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation
JP5050303B2 (ja) * 2001-06-29 2012-10-17 富士通セミコンダクター株式会社 半導体試験装置
US6651227B2 (en) * 2001-10-22 2003-11-18 Motorola, Inc. Method for generating transition delay fault test patterns
US7039845B2 (en) * 2002-03-28 2006-05-02 Jeff Rearick Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faults

Also Published As

Publication number Publication date
TW200506402A (en) 2005-02-16
CN1791942B (zh) 2010-10-13
US20070067706A1 (en) 2007-03-22
WO2004105043A1 (en) 2004-12-02
EP1629505A1 (de) 2006-03-01
KR20060014057A (ko) 2006-02-14
US7392465B2 (en) 2008-06-24
JP2007505439A (ja) 2007-03-08
CN1791942A (zh) 2006-06-21
TWI330717B (en) 2010-09-21
EP1629505B1 (de) 2009-07-15

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