DE602004016671D1 - Testvorrichtung - Google Patents

Testvorrichtung

Info

Publication number
DE602004016671D1
DE602004016671D1 DE602004016671T DE602004016671T DE602004016671D1 DE 602004016671 D1 DE602004016671 D1 DE 602004016671D1 DE 602004016671 T DE602004016671 T DE 602004016671T DE 602004016671 T DE602004016671 T DE 602004016671T DE 602004016671 D1 DE602004016671 D1 DE 602004016671D1
Authority
DE
Germany
Prior art keywords
test device
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004016671T
Other languages
English (en)
Inventor
Hironori Kanbayashi
Koichi Yatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE602004016671D1 publication Critical patent/DE602004016671D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928—Formatter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE602004016671T 2003-09-12 2004-09-10 Testvorrichtung Active DE602004016671D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003322092A JP4332392B2 (ja) 2003-09-12 2003-09-12 試験装置
PCT/JP2004/013232 WO2005026755A1 (ja) 2003-09-12 2004-09-10 試験装置

Publications (1)

Publication Number Publication Date
DE602004016671D1 true DE602004016671D1 (de) 2008-10-30

Family

ID=34308660

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004016671T Active DE602004016671D1 (de) 2003-09-12 2004-09-10 Testvorrichtung

Country Status (8)

Country Link
US (1) US7142003B2 (de)
EP (1) EP1666896B1 (de)
JP (1) JP4332392B2 (de)
KR (1) KR20060133526A (de)
CN (1) CN100523848C (de)
DE (1) DE602004016671D1 (de)
TW (1) TW200532224A (de)
WO (1) WO2005026755A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602004010287T2 (de) * 2003-09-03 2008-11-06 Advantest Corp. Testvorrichtung
DE10359806A1 (de) 2003-12-19 2005-07-14 Modine Manufacturing Co., Racine Wärmeübertrager mit flachen Rohren und flaches Wärmeübertragerrohr
JP4721762B2 (ja) * 2005-04-25 2011-07-13 株式会社アドバンテスト 試験装置
US20090250201A1 (en) 2008-04-02 2009-10-08 Grippe Frank M Heat exchanger having a contoured insert and method of assembling the same
US8424592B2 (en) 2007-01-23 2013-04-23 Modine Manufacturing Company Heat exchanger having convoluted fin end and method of assembling the same
US7620861B2 (en) * 2007-05-31 2009-11-17 Kingtiger Technology (Canada) Inc. Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
US7757144B2 (en) * 2007-11-01 2010-07-13 Kingtiger Technology (Canada) Inc. System and method for testing integrated circuit modules comprising a plurality of integrated circuit devices
US7848899B2 (en) * 2008-06-09 2010-12-07 Kingtiger Technology (Canada) Inc. Systems and methods for testing integrated circuit devices
US8356215B2 (en) * 2010-01-19 2013-01-15 Kingtiger Technology (Canada) Inc. Testing apparatus and method for analyzing a memory module operating within an application system
US8918686B2 (en) 2010-08-18 2014-12-23 Kingtiger Technology (Canada) Inc. Determining data valid windows in a system and method for testing an integrated circuit device
US8839057B2 (en) * 2011-02-03 2014-09-16 Arm Limited Integrated circuit and method for testing memory on the integrated circuit
US9003256B2 (en) 2011-09-06 2015-04-07 Kingtiger Technology (Canada) Inc. System and method for testing integrated circuits by determining the solid timing window
US8724408B2 (en) 2011-11-29 2014-05-13 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
KR101456028B1 (ko) * 2013-07-31 2014-11-03 주식회사 유니테스트 Ｆｐｇａ기반 메모리 시험 장치의 출력신호 교정 장치 및 그 방법
JP2015076110A (ja) * 2013-10-08 2015-04-20 マイクロン テクノロジー， インク． 半導体装置及びこれを備えるデータ処理システム
EP3553542A1 (de) * 2018-04-13 2019-10-16 General Electric Technology GmbH Testanordnung

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2563853A (en) * 1948-04-21 1951-08-14 Ramsey Corp Piston packing ring
JP2510973B2 (ja) * 1985-02-01 1996-06-26 株式会社日立製作所 半導体試験装置
US4615531A (en) * 1985-02-19 1986-10-07 Green George D Double ring piston sealing arrangement
US5113747A (en) * 1989-01-23 1992-05-19 Pignerol Herve Y High pressure piston sealing system and method of its assembly
JP3050391B2 (ja) * 1990-01-22 2000-06-12 日立電子エンジニアリング株式会社 Ｉｃテスタのテスト波形発生装置
JP2590741Y2 (ja) * 1993-10-18 1999-02-17 株式会社アドバンテスト 半導体試験装置用タイミング発生器
US6263463B1 (en) * 1996-05-10 2001-07-17 Advantest Corporation Timing adjustment circuit for semiconductor test system
US5794175A (en) * 1997-09-09 1998-08-11 Teradyne, Inc. Low cost, highly parallel memory tester
GB9805124D0 (en) * 1998-03-10 1998-05-06 Compair Reavell Ltd Piston sealing ring assembly
JPH11264857A (ja) * 1998-03-19 1999-09-28 Advantest Corp 半導体試験装置
US6058055A (en) * 1998-03-31 2000-05-02 Micron Electronics, Inc. System for testing memory
JPH11304888A (ja) * 1998-04-17 1999-11-05 Advantest Corp 半導体試験装置
US6452411B1 (en) * 1999-03-01 2002-09-17 Formfactor, Inc. Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses
US6466007B1 (en) * 2000-08-14 2002-10-15 Teradyne, Inc. Test system for smart card and indentification devices and the like
US6304119B1 (en) * 2000-12-27 2001-10-16 Chroma Ate Inc. Timing generating apparatus with self-calibrating capability
WO2002075336A2 (en) * 2001-03-20 2002-09-26 Nptest, Inc. Test system algorithmic program generators
DE10131712B4 (de) * 2001-06-29 2009-04-09 Qimonda Ag Elektronisches Bauelement, Testereinrichtung und Verfahren zur Kalibrierung einer Testereinrichtung
JP2003098222A (ja) * 2001-09-25 2003-04-03 Mitsubishi Electric Corp 検査用基板、検査装置及び半導体装置の検査方法
KR100487946B1 (ko) * 2002-08-29 2005-05-06 삼성전자주식회사 반도체 테스트 시스템 및 이 시스템의 테스트 방법
JP4173726B2 (ja) * 2002-12-17 2008-10-29 株式会社ルネサステクノロジ インターフェイス回路
US7290192B2 (en) * 2003-03-31 2007-10-30 Advantest Corporation Test apparatus and test method for testing plurality of devices in parallel

Also Published As

Publication number Publication date
JP4332392B2 (ja) 2009-09-16
TW200532224A (en) 2005-10-01
EP1666896B1 (de) 2008-09-17
EP1666896A1 (de) 2006-06-07
KR20060133526A (ko) 2006-12-26
TWI339735B (de) 2011-04-01
WO2005026755A1 (ja) 2005-03-24
CN1829918A (zh) 2006-09-06
CN100523848C (zh) 2009-08-05
EP1666896A4 (de) 2006-10-04
US7142003B2 (en) 2006-11-28
US20050138505A1 (en) 2005-06-23
JP2005091038A (ja) 2005-04-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition