DE602004013346D1 - Aktive pullup-vorrichtung für einen datenbus - Google Patents

Aktive pullup-vorrichtung für einen datenbus

Info

Publication number
DE602004013346D1
DE602004013346D1 DE602004013346T DE602004013346T DE602004013346D1 DE 602004013346 D1 DE602004013346 D1 DE 602004013346D1 DE 602004013346 T DE602004013346 T DE 602004013346T DE 602004013346 T DE602004013346 T DE 602004013346T DE 602004013346 D1 DE602004013346 D1 DE 602004013346D1
Authority
DE
Germany
Prior art keywords
data bus
pullup device
active pullup
active
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004013346T
Other languages
English (en)
Other versions
DE602004013346T2 (de
Inventor
William John Testin
David Gene Novak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Publication of DE602004013346D1 publication Critical patent/DE602004013346D1/de
Application granted granted Critical
Publication of DE602004013346T2 publication Critical patent/DE602004013346T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Power Sources (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Information Transfer Systems (AREA)
DE602004013346T 2003-09-09 2004-09-09 Aktive pullup-vorrichtung für einen datenbus Active DE602004013346T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US50189403P 2003-09-09 2003-09-09
US501894P 2003-09-09
PCT/US2004/029522 WO2005024642A2 (en) 2003-09-09 2004-09-09 Active pull up apparatus for a data bus

Publications (2)

Publication Number Publication Date
DE602004013346D1 true DE602004013346D1 (de) 2008-06-05
DE602004013346T2 DE602004013346T2 (de) 2009-07-09

Family

ID=34273075

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004013346T Active DE602004013346T2 (de) 2003-09-09 2004-09-09 Aktive pullup-vorrichtung für einen datenbus

Country Status (9)

Country Link
US (1) US7459939B2 (de)
EP (1) EP1665060B1 (de)
JP (1) JP2007505375A (de)
KR (1) KR101129006B1 (de)
CN (1) CN100472495C (de)
BR (1) BRPI0413824A (de)
DE (1) DE602004013346T2 (de)
ES (1) ES2308253T3 (de)
WO (1) WO2005024642A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106612377B (zh) * 2017-01-12 2019-09-27 维沃移动通信有限公司 一种控制双摄像头的电路、移动终端和方法
CN108134599B (zh) * 2017-12-04 2019-03-08 山东高云半导体科技有限公司 一种i3c总线控制接口电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272396B2 (en) * 1991-09-05 1996-11-26 Unitrode Corp Controllable bus terminator with voltage regulation
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US5336948A (en) * 1992-12-16 1994-08-09 Unitrode Corporation Active negation emulator
JP3698439B2 (ja) * 1994-12-02 2005-09-21 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴイ データ通信バスを有する回路
US5635852A (en) * 1995-04-17 1997-06-03 Linfinity Microelectronics, Inc. Controllable actice terminator for a computer bus
DE19611945C1 (de) * 1996-03-26 1997-11-20 Daimler Benz Ag Einrichtung für den busvernetzten Betrieb eines elektronischen Gerätes mit Microcontroller sowie deren Verwendung
JP3400294B2 (ja) * 1997-04-25 2003-04-28 富士通株式会社 プル・アップ回路及び半導体装置
US6005432A (en) * 1998-04-01 1999-12-21 S3 Incorporated Voltage level shift system and method
US6181193B1 (en) * 1999-10-08 2001-01-30 International Business Machines Corporation Using thick-oxide CMOS devices to interface high voltage integrated circuits
US6356106B1 (en) * 2000-09-12 2002-03-12 Micron Technology, Inc. Active termination in a multidrop memory system
JP3664236B2 (ja) * 2000-10-30 2005-06-22 ティアック株式会社 Ｕｓｂ機器
US6781415B2 (en) * 2001-11-27 2004-08-24 Fairchild Semiconductor Corporation Active voltage level bus switch (or pass gate) translator
US6771095B1 (en) * 2002-11-22 2004-08-03 Analog Devices, Inc. Level translating digital switch
JP4345471B2 (ja) * 2003-12-18 2009-10-14 セイコーエプソン株式会社 物理層回路、データ転送制御装置、及び電子機器

Also Published As

Publication number Publication date
ES2308253T3 (es) 2008-12-01
DE602004013346T2 (de) 2009-07-09
EP1665060A2 (de) 2006-06-07
BRPI0413824A (pt) 2006-10-24
EP1665060B1 (de) 2008-04-23
CN100472495C (zh) 2009-03-25
WO2005024642A3 (en) 2005-06-23
KR20070037561A (ko) 2007-04-05
WO2005024642A2 (en) 2005-03-17
CN1849595A (zh) 2006-10-18
US20060290811A1 (en) 2006-12-28
US7459939B2 (en) 2008-12-02
KR101129006B1 (ko) 2012-03-27
JP2007505375A (ja) 2007-03-08

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition