DE602004013292D1 - Verfahren zur Herstellung eines Verbundsubstrats - Google Patents

Verfahren zur Herstellung eines Verbundsubstrats

Info

Publication number
DE602004013292D1
DE602004013292D1 DE602004013292T DE602004013292T DE602004013292D1 DE 602004013292 D1 DE602004013292 D1 DE 602004013292D1 DE 602004013292 T DE602004013292 T DE 602004013292T DE 602004013292 T DE602004013292 T DE 602004013292T DE 602004013292 D1 DE602004013292 D1 DE 602004013292D1
Authority
DE
Germany
Prior art keywords
material compound
source substrate
thermal annealing
splitting area
predetermined splitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004013292T
Other languages
English (en)
Other versions
DE602004013292T2 (de
Inventor
Thibaut Maurice
Eric Guiot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of DE602004013292D1 publication Critical patent/DE602004013292D1/de
Application granted granted Critical
Publication of DE602004013292T2 publication Critical patent/DE602004013292T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Recrystallisation Techniques (AREA)
  • Investigating Or Analysing Materials By Optical Means (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
  • Laminated Bodies (AREA)
DE602004013292T 2004-06-11 2004-06-11 Verfahren zur Herstellung eines Verbundsubstrats Expired - Lifetime DE602004013292T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04291472A EP1605505B1 (de) 2004-06-11 2004-06-11 Verfahren zur Herstellung eines Verbundsubstrats

Publications (2)

Publication Number Publication Date
DE602004013292D1 true DE602004013292D1 (de) 2008-06-05
DE602004013292T2 DE602004013292T2 (de) 2009-05-28

Family

ID=34931172

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004013292T Expired - Lifetime DE602004013292T2 (de) 2004-06-11 2004-06-11 Verfahren zur Herstellung eines Verbundsubstrats

Country Status (5)

Country Link
US (2) US7217639B2 (de)
EP (1) EP1605505B1 (de)
JP (1) JP4343148B2 (de)
AT (1) ATE393473T1 (de)
DE (1) DE602004013292T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5044195B2 (ja) * 2006-11-10 2012-10-10 信越化学工業株式会社 Ｓｏｑ基板の製造方法
FR2914488B1 (fr) * 2007-03-30 2010-08-27 Soitec Silicon On Insulator Substrat chauffage dope
FR2915625B1 (fr) * 2007-04-27 2009-10-02 Soitec Silicon On Insulator Procede de transfert d'une couche epitaxiale
EP2103632A1 (de) * 2008-03-20 2009-09-23 Ineos Europe Limited Polimerisationsverfahren
US8698106B2 (en) * 2008-04-28 2014-04-15 Varian Semiconductor Equipment Associates, Inc. Apparatus for detecting film delamination and a method thereof
FR3132787A1 (fr) * 2022-02-14 2023-08-18 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de suivi de fragilisation d’une interface entre un substrat et une couche et dispositif permettant un tel suivi

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213652A (ja) * 1996-02-01 1997-08-15 Semiconductor Energy Lab Co Ltd レーザーアニール装置
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6166354A (en) * 1997-06-16 2000-12-26 Advanced Micro Devices, Inc. System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication
FR2767416B1 (fr) 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US6425971B1 (en) * 2000-05-10 2002-07-30 Silverbrook Research Pty Ltd Method of fabricating devices incorporating microelectromechanical systems using UV curable tapes
US20040087042A1 (en) * 2002-08-12 2004-05-06 Bruno Ghyselen Method and apparatus for adjusting the thickness of a layer of semiconductor material
EP1429381B1 (de) * 2002-12-10 2011-07-06 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung eines Verbundmaterials

Also Published As

Publication number Publication date
US7217639B2 (en) 2007-05-15
JP2006041488A (ja) 2006-02-09
ATE393473T1 (de) 2008-05-15
JP4343148B2 (ja) 2009-10-14
EP1605505B1 (de) 2008-04-23
EP1605505A1 (de) 2005-12-14
DE602004013292T2 (de) 2009-05-28
US20070105246A1 (en) 2007-05-10
US20050277269A1 (en) 2005-12-15

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