DE60142424D1 - Hochspannungshalbleiteranordnungsabschluss - Google Patents

Hochspannungshalbleiteranordnungsabschluss

Info

Publication number
DE60142424D1
DE60142424D1 DE60142424T DE60142424T DE60142424D1 DE 60142424 D1 DE60142424 D1 DE 60142424D1 DE 60142424 T DE60142424 T DE 60142424T DE 60142424 T DE60142424 T DE 60142424T DE 60142424 D1 DE60142424 D1 DE 60142424D1
Authority
DE
Germany
Prior art keywords
high voltage
semiconductor device
voltage semiconductor
varies
statements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60142424T
Other languages
English (en)
Inventor
Theodore J Letavic
Mark R Simpson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60142424D1 publication Critical patent/DE60142424D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Landscapes

  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Rectifiers (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Non-Volatile Memory (AREA)
DE60142424T 2000-03-20 2001-03-06 Hochspannungshalbleiteranordnungsabschluss Expired - Lifetime DE60142424D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/531,701 US6642558B1 (en) 2000-03-20 2000-03-20 Method and apparatus of terminating a high voltage solid state device
PCT/EP2001/002531 WO2001071810A2 (en) 2000-03-20 2001-03-06 High voltage solid state device termination

Publications (1)

Publication Number Publication Date
DE60142424D1 true DE60142424D1 (de) 2010-08-05

Family

ID=24118686

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60142424T Expired - Lifetime DE60142424D1 (de) 2000-03-20 2001-03-06 Hochspannungshalbleiteranordnungsabschluss

Country Status (6)

Country Link
US (2) US6642558B1 (de)
EP (1) EP1186050B1 (de)
JP (1) JP2003528470A (de)
AT (1) ATE472174T1 (de)
DE (1) DE60142424D1 (de)
WO (1) WO2001071810A2 (de)

Families Citing this family (11)

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US6231825B1 (en) 1999-07-29 2001-05-15 Rohm And Haas Company Production of sodium borohydride from sodium borohydride dihydrate in a fluidized bed dryer
GB2373634B (en) * 2000-10-31 2004-12-08 Fuji Electric Co Ltd Semiconductor device
US7037814B1 (en) * 2003-10-10 2006-05-02 National Semiconductor Corporation Single mask control of doping levels
WO2006098728A2 (en) * 2005-03-11 2006-09-21 Amerisource Companies, Lp Method and system for item delivery
US9679602B2 (en) 2006-06-14 2017-06-13 Seagate Technology Llc Disc drive circuitry swap
US9305590B2 (en) 2007-10-16 2016-04-05 Seagate Technology Llc Prevent data storage device circuitry swap
US8101997B2 (en) 2008-04-29 2012-01-24 Infineon Technologies Austria Ag Semiconductor device with a charge carrier compensation structure in a semiconductor body and method for its production
US8154078B2 (en) * 2010-02-17 2012-04-10 Vanguard International Semiconductor Corporation Semiconductor structure and fabrication method thereof
US9306034B2 (en) 2014-02-24 2016-04-05 Vanguard International Semiconductor Corporation Method and apparatus for power device with multiple doped regions
DE102015208097B4 (de) 2015-04-30 2022-03-31 Infineon Technologies Ag Herstellen einer Halbleitervorrichtung durch Epitaxie
CN108369963B (zh) * 2015-12-15 2022-01-25 通用电气公司 碳化硅超结功率器件的边缘终端设计

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GB1558506A (en) * 1976-08-09 1980-01-03 Mullard Ltd Semiconductor devices having a rectifying metalto-semicondductor junction
GB2089119A (en) 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
GB2104287B (en) * 1981-08-21 1985-02-20 Gen Electric Co Plc Data storage devices
GB2131603B (en) * 1982-12-03 1985-12-18 Philips Electronic Associated Semiconductor devices
DE3581348D1 (de) * 1984-09-28 1991-02-21 Siemens Ag Verfahren zum herstellen eines pn-uebergangs mit hoher durchbruchsspannung.
JPH0644578B2 (ja) * 1984-12-21 1994-06-08 三菱電機株式会社 電荷転送素子
US4648174A (en) * 1985-02-05 1987-03-10 General Electric Company Method of making high breakdown voltage semiconductor device
DE3715675A1 (de) * 1987-05-11 1988-12-01 Messerschmitt Boelkow Blohm Halbleiterelement
US4927772A (en) * 1989-05-30 1990-05-22 General Electric Company Method of making high breakdown voltage semiconductor device
DE69209678T2 (de) * 1991-02-01 1996-10-10 Philips Electronics Nv Halbleiteranordnung für Hochspannungsverwendung und Verfahren zur Herstellung
JP3192809B2 (ja) * 1993-03-12 2001-07-30 株式会社東芝 高耐圧炭化珪素ショットキ−・ダイオ−ド
EP0661753A1 (de) * 1994-01-04 1995-07-05 Motorola, Inc. Halbleiterstruktur mit feldsbegrenzender Zone und Verfahren zur Herstellung
US5486718A (en) * 1994-07-05 1996-01-23 Motorola, Inc. High voltage planar edge termination structure and method of making same
DE69525003T2 (de) * 1994-08-15 2003-10-09 Siliconix Inc Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken
US5967795A (en) * 1995-08-30 1999-10-19 Asea Brown Boveri Ab SiC semiconductor device comprising a pn junction with a voltage absorbing edge
KR970024275A (ko) * 1995-10-10 1997-05-30 김광호 안전 동작 영역을 증가시킨 트랜지스터 및 그 제조 방법
US5940721A (en) * 1995-10-11 1999-08-17 International Rectifier Corporation Termination structure for semiconductor devices and process for manufacture thereof
US6037632A (en) 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
DE59711481D1 (de) 1996-02-05 2004-05-06 Infineon Technologies Ag Durch Feldeffekt steuerbares Halbleiterbauelement
JPH09268202A (ja) * 1996-03-29 1997-10-14 Mitsubishi Rayon Co Ltd シラップおよびその製造方法
US6002159A (en) * 1996-07-16 1999-12-14 Abb Research Ltd. SiC semiconductor device comprising a pn junction with a voltage absorbing edge
JP3632344B2 (ja) * 1997-01-06 2005-03-23 日産自動車株式会社 半導体装置
SE9700156D0 (sv) * 1997-01-21 1997-01-21 Abb Research Ltd Junction termination for Si C Schottky diode
US5932894A (en) * 1997-06-26 1999-08-03 Abb Research Ltd. SiC semiconductor device comprising a pn junction
WO1999023703A1 (de) 1997-11-03 1999-05-14 Infineon Technologies Ag Hochspannungsfeste randstruktur für halbleiterbauelemente
SE512259C2 (sv) * 1998-03-23 2000-02-21 Abb Research Ltd Halvledaranordning bestående av dopad kiselkarbid vilken innefattar en pn-övergång som uppvisar åtminstone en ihålig defekt och förfarande för dess framställning
WO1999053550A1 (de) 1998-04-08 1999-10-21 Siemens Aktiengesellschaft Hochvolt-randabschluss für planarstrukturen
DE19816448C1 (de) * 1998-04-14 1999-09-30 Siemens Ag Universal-Halbleiterscheibe für Hochspannungs-Halbleiterbauelemente, ihr Herstellungsverfahren und ihre Verwendung
US6096663A (en) * 1998-07-20 2000-08-01 Philips Electronics North America Corporation Method of forming a laterally-varying charge profile in silicon carbide substrate
US6355508B1 (en) * 1998-09-02 2002-03-12 Micron Technology, Inc. Method for forming electrostatic discharge protection device having a graded junction
DE19843659A1 (de) * 1998-09-23 2000-04-06 Siemens Ag Halbleiterbauelement mit strukturiertem Halbleiterkörper
EP1011146B1 (de) * 1998-12-09 2006-03-08 STMicroelectronics S.r.l. Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen

Also Published As

Publication number Publication date
US6927103B2 (en) 2005-08-09
EP1186050A1 (de) 2002-03-13
US6642558B1 (en) 2003-11-04
WO2001071810A3 (en) 2002-01-03
ATE472174T1 (de) 2010-07-15
US20040104430A1 (en) 2004-06-03
EP1186050B1 (de) 2010-06-23
WO2001071810A2 (en) 2001-09-27
JP2003528470A (ja) 2003-09-24

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