WO2001071810A2 - High voltage solid state device termination - Google Patents

High voltage solid state device termination Download PDF

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Publication number
WO2001071810A2
WO2001071810A2 PCT/EP2001/002531 EP0102531W WO0171810A2 WO 2001071810 A2 WO2001071810 A2 WO 2001071810A2 EP 0102531 W EP0102531 W EP 0102531W WO 0171810 A2 WO0171810 A2 WO 0171810A2
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WO
WIPO (PCT)
Prior art keywords
charge
termination region
layer
region
layers
Prior art date
Application number
PCT/EP2001/002531
Other languages
French (fr)
Other versions
WO2001071810A3 (en
Inventor
Theodore J. Letavic
Mark R. Simpson
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to AT01907578T priority Critical patent/ATE472174T1/en
Priority to JP2001569891A priority patent/JP2003528470A/en
Priority to EP01907578A priority patent/EP1186050B1/en
Priority to DE60142424T priority patent/DE60142424D1/en
Publication of WO2001071810A2 publication Critical patent/WO2001071810A2/en
Publication of WO2001071810A3 publication Critical patent/WO2001071810A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Definitions

  • This invention relates to electronics, and more specifically, to an improved technique of terminating a solid state device.
  • the invention has particular application in high voltage termination of charge compensated devices.
  • Fig. 1 shows a side cross sectional view of an exemplary prior art VDMOS device.
  • P doped regions 109 are repetitive along a top surface 114 and are typically kept at approximately ground voltage during operation of the device.
  • the gate 1 11 may be operated at a conventional value of, for example, 15 volts.
  • At the lower surface of the device is the 600 volt terminal 113.
  • the voltage may ⁇ se to 1000 V or more.
  • a region 107 is denoted T for termination, and must drop the 600 volts across the width of the region.
  • T 107 may be on the order of 50 microns.
  • FIG. 2 A top view of the arrangement of Fig. 1 is shown in Fig. 2.
  • the border region 107 is the termination region, which must include some type of structure for dropping the 600 volts across only 50 micrometers
  • Section 105 represents the active region of the device
  • Fig 3 shows a typical p ⁇ or art structure for providing termination of such a high voltage device.
  • a set of floating guard ⁇ ngs 302 is used to control the electric field dist ⁇ bution around the device pe ⁇ phery.
  • the number of ⁇ ngs in the structure depends on the voltage rating of the device. For example, 8 rings are used for a 1,000 volt device.
  • a three dimensional computer model enables the optimum ⁇ ng spacing to be determined so that each ring expe ⁇ ences a similar field intensity as the structure approaches avalanche breakdown
  • the ⁇ ngs are passivated with polydox (oxygen-doped polycrystalhne silicon), which acts as an electrostatic screen and prevents external ionic charges inverting the lightly doped N- lnterface to form P- channels between the rings.
  • the polydox is coated with layers of silicon nit ⁇ de and phosphorous doped oxide, as shown
  • the surface area of the termination region of the device represents a source of added cost to the device. Specifically, the termination region is a substantial sized lateral width that must wrap entirely around the periphery of the device. This increases the cost of the device, and over the large number of chips per wafer, becomes a significant source of wasted cost and space.
  • a multiple layer solid state device is constructed wherein each layer includes a varying charge profile extending laterally through the termination region, from the edge of the active (drift) region extending laterally towards the edge of the crystal.
  • the charge profile represents the density of deposited charge as a specified cross section is traversed.
  • the charge profile is different in different layers, so that each layer of the multiple layer device includes decreasing charge density as the termination layer is traversed laterally.
  • a decreasing charge profile is also exhibited as a vertical cross section is traversed upwardly towards the source region of the device.
  • the charge profile decreases substantially linearly along any cross section, lateral or vertical, resulting in a substantially uniform value of electric field strength.
  • a preferred method of making the device comprises depositing volumes of charge along each layer in a multiple layer device, in the termination region.
  • the volume of charge in each deposit (i.e., dot) or the spacing between the deposits may be varied, with such variation being different at different layers. This causes the field strength to remain substantially constant along any horizontal or vertical cross section.
  • FIG. 1 is a cross sectional view of a semiconductor device, depicting the need for termination
  • Fig. 2 is a top view of the arrangement of Fig. 1 ;
  • Fig. 3 shows a prior art termination technique utilizing several floating P rings
  • Fig. 4 is a conceptual representation of charge profiles in a semiconductor device, the charge profiles varying in accordance with the present invention
  • Fig. 5 is an alternative embodiment of the present invention.
  • Fig. 4 shows a conceptual diagram of a cross section through a multi layer device fabricated in accordance with the teachings of the present invention. While layers 403, 405, and 407 are shown, further layers are possible. Region 421 represents the active region of the device, and region 422 represents the termination region of the device. That active region may be constructed to behave electrically as any one or more of a variety of such devices, and is not critical to the present invention. Thus, we only discuss the termination region hereafter.
  • Layers 403, 405 and 407 each include a charge profile which decreases as the layer is traversed laterally from region 421 to the outside of the device.
  • the charge profile is constructed, in the arrangement of Fig. 4, such that the total charge is a function of lateral or vertical position. Hence, as shown in Fig. 4, more charge is deposited at 409 than at 411, and more charge is deposited at 411 than at 413, and even less charge is deposited at 415.
  • the charge profile includes columns 409, 411 , 413, and 415.
  • the successive reduction of total charge with linear dependence on position results in an electric field strength which is substantially constant over a lateral/vertical section.
  • One way of accomplishing the decreasing charge profile uses the same mask as used for fabrication of the active device.
  • the mask has a portion that extends over the termination region. That extended portion has plural openings which get smaller as one moves away from the active region.
  • the discrete deposits of charge i.e., charge dots
  • a similar decrease in charge is encountered as a vertical cross section is traversed. Specifically, looking only at column 409 of Fig. 4, as one traverses upward from row 403 to 405 to 407, less charge is deposited with each discrete deposit.
  • the size of the openings in the mask used for each layer may vary, as depicted in Fig. 4.
  • the small rectangles represent a three by four matrix of discrete deposits of charge, each of which has a different volume of charge contained therein.
  • a typical geometry for such openings may range from approximately 2.5 to 40 microns squared.
  • the electric field strength at any position within the termination region can be calculated from the spatial variation of charge.
  • a desired electric field strength can be realized by judicious design of the charge profile.
  • the lateral charge at any point in the termination region can be obtained by summing the contribution from each discrete charge region, subjected to a specified thermal anneal or drive. It is well known to those of skill in the art how to calculate a charge profile for a desired field strength, and how to calculate the field strength from the desired charge profile.
  • the approximately 600 volts in the exemplary embodiment used herein must also be dropped from the bottom to the surface of the device.
  • the same procedure is utilized upwardly along any column, in order to drop 600 volts across N layers, for devices of N layers deep.
  • the invention may be fabricated in a convenient manner for multi layer devices. Specifically, in such multi layer devices the layers are each fabricated separately using a particular mask. The same masks can be utilized to lay down the termination region, with holes of varying size allowing for different amounts of charge. Notably, the mask for each layer would be different, since the openings in the mask that allow for the deposit of charge in the termination region are different. Thus, it is possible to have N different masks, one for each layer.
  • the portion of the mask that corresponds to the active region may be the same for each mask, and the portion that corresponds to the termination region is different for each mask, in order to vary the profile.
  • Fig. 5 shows a slightly different embodiment for accomplishing a similar objective as Fig. 4.
  • the size of the discrete charge deposits is similar to each other.
  • the distance between such discrete deposits varies as the termination region is laterally traversed.
  • the same varying spacing can be found as a vertical cross section is traversed.
  • distance 505 would be slightly less than distance 506.
  • the same substantially constant electric field can be implemented by depositing the discrete charge deposits in equal amounts but further and further apart, as the cross section is traversed, rather than depositing the charge dots in less and less quantity at a fixed distance.
  • a combination approach may be used as well, where the volume of charge in each deposit and the spacing are varied.
  • the charge should be deposited in a manner that decreases with distance from the active (drift) region in a substantially linear manner. This causes a substantially constant electric field strength as one moves away from the active region. That means that the charge in each dot should decrease linearly with distance from the active region.

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  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
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Abstract

Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between different layers of a multiple layer device. In a preferred embodiment, the variations are such that the field strength is substantially constant along any horizontal or vertical cross section of the termination region.

Description

High voltage solid state device termination
This invention relates to electronics, and more specifically, to an improved technique of terminating a solid state device. The invention has particular application in high voltage termination of charge compensated devices.
Fig. 1 shows a side cross sectional view of an exemplary prior art VDMOS device. As indicated therein, P doped regions 109 are repetitive along a top surface 114 and are typically kept at approximately ground voltage during operation of the device. The gate 1 11 may be operated at a conventional value of, for example, 15 volts. At the lower surface of the device is the 600 volt terminal 113. As a result of the structure of the device, that voltage appears at point 103 since point 103 is not electrically isolated from the bottom terminal 113 of the device having the 600 volts. In similar devices, the voltage may πse to 1000 V or more.
A region 107 is denoted T for termination, and must drop the 600 volts across the width of the region. In practical devices, T 107 may be on the order of 50 microns.
A top view of the arrangement of Fig. 1 is shown in Fig. 2. The border region 107 is the termination region, which must include some type of structure for dropping the 600 volts across only 50 micrometers Section 105 represents the active region of the device
Fig 3 shows a typical pπor art structure for providing termination of such a high voltage device. A set of floating guard πngs 302 is used to control the electric field distπbution around the device peπphery. The number of πngs in the structure depends on the voltage rating of the device. For example, 8 rings are used for a 1,000 volt device. A three dimensional computer model enables the optimum πng spacing to be determined so that each ring expeπences a similar field intensity as the structure approaches avalanche breakdown The πngs are passivated with polydox (oxygen-doped polycrystalhne silicon), which acts as an electrostatic screen and prevents external ionic charges inverting the lightly doped N- lnterface to form P- channels between the rings. The polydox is coated with layers of silicon nitπde and phosphorous doped oxide, as shown The surface area of the termination region of the device represents a source of added cost to the device. Specifically, the termination region is a substantial sized lateral width that must wrap entirely around the periphery of the device. This increases the cost of the device, and over the large number of chips per wafer, becomes a significant source of wasted cost and space.
In view of the foregoing, there exists a need in the art for an improved technique of terminating high voltage semiconductor devices without utilizing the relatively large amount of surface area.
There also exists a need for a technique of fabricating a termination structure that is easily manufactured, and does not add significant costs to the device manufacturing procedure.
The above and other problems of the prior art are addressed in accordance with the present invention. A multiple layer solid state device is constructed wherein each layer includes a varying charge profile extending laterally through the termination region, from the edge of the active (drift) region extending laterally towards the edge of the crystal.
The charge profile, as defined herein, represents the density of deposited charge as a specified cross section is traversed. In a preferred embodiment, the charge profile is different in different layers, so that each layer of the multiple layer device includes decreasing charge density as the termination layer is traversed laterally. Moreover, a decreasing charge profile is also exhibited as a vertical cross section is traversed upwardly towards the source region of the device. In a preferred embodiment, the charge profile decreases substantially linearly along any cross section, lateral or vertical, resulting in a substantially uniform value of electric field strength.
A preferred method of making the device comprises depositing volumes of charge along each layer in a multiple layer device, in the termination region. The volume of charge in each deposit (i.e., dot) or the spacing between the deposits may be varied, with such variation being different at different layers. This causes the field strength to remain substantially constant along any horizontal or vertical cross section.
A further understanding will be gained by reference to the accompanying drawings and description. Fig. 1 is a cross sectional view of a semiconductor device, depicting the need for termination;
Fig. 2 is a top view of the arrangement of Fig. 1 ;
Fig. 3 shows a prior art termination technique utilizing several floating P rings;
Fig. 4 is a conceptual representation of charge profiles in a semiconductor device, the charge profiles varying in accordance with the present invention;
Fig. 5 is an alternative embodiment of the present invention.
Fig. 4 shows a conceptual diagram of a cross section through a multi layer device fabricated in accordance with the teachings of the present invention. While layers 403, 405, and 407 are shown, further layers are possible. Region 421 represents the active region of the device, and region 422 represents the termination region of the device. That active region may be constructed to behave electrically as any one or more of a variety of such devices, and is not critical to the present invention. Thus, we only discuss the termination region hereafter.
Layers 403, 405 and 407 each include a charge profile which decreases as the layer is traversed laterally from region 421 to the outside of the device. The charge profile is constructed, in the arrangement of Fig. 4, such that the total charge is a function of lateral or vertical position. Hence, as shown in Fig. 4, more charge is deposited at 409 than at 411, and more charge is deposited at 411 than at 413, and even less charge is deposited at 415. The charge profile includes columns 409, 411 , 413, and 415. The successive reduction of total charge with linear dependence on position results in an electric field strength which is substantially constant over a lateral/vertical section. One way of accomplishing the decreasing charge profile uses the same mask as used for fabrication of the active device. The mask has a portion that extends over the termination region. That extended portion has plural openings which get smaller as one moves away from the active region. Thus, the discrete deposits of charge (i.e., charge dots) diminish in size, as the distance from the active region becomes greater, resulting in a substantially constant electric field.
Additionally, a similar decrease in charge is encountered as a vertical cross section is traversed. Specifically, looking only at column 409 of Fig. 4, as one traverses upward from row 403 to 405 to 407, less charge is deposited with each discrete deposit. The size of the openings in the mask used for each layer may vary, as depicted in Fig. 4. The small rectangles represent a three by four matrix of discrete deposits of charge, each of which has a different volume of charge contained therein. A typical geometry for such openings may range from approximately 2.5 to 40 microns squared.
The electric field strength at any position within the termination region can be calculated from the spatial variation of charge. Alternatively, a desired electric field strength can be realized by judicious design of the charge profile. The lateral charge at any point in the termination region can be obtained by summing the contribution from each discrete charge region, subjected to a specified thermal anneal or drive. It is well known to those of skill in the art how to calculate a charge profile for a desired field strength, and how to calculate the field strength from the desired charge profile.
Moreover, from Fig. 1 it can be seen that the approximately 600 volts in the exemplary embodiment used herein must also be dropped from the bottom to the surface of the device. The same procedure is utilized upwardly along any column, in order to drop 600 volts across N layers, for devices of N layers deep. Notably, the invention may be fabricated in a convenient manner for multi layer devices. Specifically, in such multi layer devices the layers are each fabricated separately using a particular mask. The same masks can be utilized to lay down the termination region, with holes of varying size allowing for different amounts of charge. Notably, the mask for each layer would be different, since the openings in the mask that allow for the deposit of charge in the termination region are different. Thus, it is possible to have N different masks, one for each layer. The portion of the mask that corresponds to the active region may be the same for each mask, and the portion that corresponds to the termination region is different for each mask, in order to vary the profile.
Fig. 5 shows a slightly different embodiment for accomplishing a similar objective as Fig. 4. Specifically, in Fig. 5, the size of the discrete charge deposits is similar to each other. However, the distance between such discrete deposits varies as the termination region is laterally traversed. Moreover, the same varying spacing can be found as a vertical cross section is traversed. For example, distance 505 would be slightly less than distance 506. Accordingly, the same substantially constant electric field can be implemented by depositing the discrete charge deposits in equal amounts but further and further apart, as the cross section is traversed, rather than depositing the charge dots in less and less quantity at a fixed distance. Of course, a combination approach may be used as well, where the volume of charge in each deposit and the spacing are varied. In the preferred embodiment, the charge should be deposited in a manner that decreases with distance from the active (drift) region in a substantially linear manner. This causes a substantially constant electric field strength as one moves away from the active region. That means that the charge in each dot should decrease linearly with distance from the active region.
While the above describes a preferred embodiment of the invention, various modifications and additions will be apparent to those of skill in the art.

Claims

CLAIMS:
1. A solid state device including a plurality of layers(403,405,407), each layer including an active region (421) and a termination region (422) at least two layers including termination regions that comprise a varying charge profile(409, 411, 413, 415) extending from the active region (421), laterally through the termination region(422) towards an edge of said termination region ( 422).
2. The device of claim 1 wherein all of said layers (403,405,407) include a varying charge profile.
3. The device of claim 1 wherein the varying charge profile (409,411,413,415) of each layer is different from said varying charge profile for other layers.
4. The device of claim 3 wherein said varying charge profile (409,411,413,415) of each layer (403,405,407) is different from said varying charge profile for other layers.
5. The device of claim 4 wherein said varying charge profile on at least one layer (403) comprises discrete deposits of charge (430,431) that vary in total volume.
6. The device of claim 4 wherein said varying charge on each layer comprises discrete deposits of charge (430,431) that vary in spacing from one another.
7. The device of claim 4 wherein said charge profile (409,411,413,415) on each layer varies substantially linearly with distance away from said active region (421).
8. The device of claim 4 wherein charge varies along a vertical cross section through multiple layers (407, 405, 403) of said termination region (422) at a fixed distance from said active region in a substantially linear manner.
9. The device of claim 7 wherein charge vanes along a vertical cross section through multiple layers of said termination region (422) at a fixed distance from said active region (421) in a substantially linear manner.
10. A solid state device having plural epitaxial layers, (403, 405, 407) each epitaxial layer including a termination region (422), the termination region being doped with a plurality of p- dots of charge (430,431) which vary along the termination region in their volume or spacing, the volume and spacing of said charge dots (430,431) being different on at least two different layers (403,405,407) of said device
11. The solid state device of claim 10 wherein the volume and spacing of the dots (430,431) on each layer is such that a substantially constant field strength is achieved moving away from the active region (421) along any layer or moving upwards through the layers (403, 405, 407) along any vertical cross section.
12. A method of constructing a solid state device compnsing the steps of: forming a first layer (403) including an active region and a termination region using a first mask; and forming at least a second layer (405) including an active region (421) and a termination region (422) using a second mask, the first and second masks being different for the portions corresponding to the termination region (422).
13. The method of claim 12 wherein the step of forming at least a second layer includes using a second mask that is substantially identical to the first mask in the portion corresponding to the active region (421).
14. A method of forming termination region for a solid state device, the termination region having a width and a depth, the method compnsing the steps of
(a) doping the termination region (422) in varying charge concentrations along the width; and
(b) doping the termination region (422) in varying charge concentrations along the depth
15. The method of claim 14 wherein the step (a) of doping includes placing discrete deposits of charge (430, 431) of varying volume along a horizontal cross section of said termination region.
16. The method of claim 14 wherein said steps (a) and (b) comprise doping in concentrations such that field strength along any horizontal or vertical cross section is no greater than 15 volts per micrometer.
PCT/EP2001/002531 2000-03-20 2001-03-06 High voltage solid state device termination WO2001071810A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AT01907578T ATE472174T1 (en) 2000-03-20 2001-03-06 HIGH VOLTAGE SEMICONDUCTOR ARRANGEMENT TERMINATION
JP2001569891A JP2003528470A (en) 2000-03-20 2001-03-06 Terminal structure of high-pressure solid equipment
EP01907578A EP1186050B1 (en) 2000-03-20 2001-03-06 High voltage solid state device termination
DE60142424T DE60142424D1 (en) 2000-03-20 2001-03-06 HIGH VOLTAGE SEMICONDUCTOR DEVICE STATEMENTS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/531,701 2000-03-20
US09/531,701 US6642558B1 (en) 2000-03-20 2000-03-20 Method and apparatus of terminating a high voltage solid state device

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WO2001071810A2 true WO2001071810A2 (en) 2001-09-27
WO2001071810A3 WO2001071810A3 (en) 2002-01-03

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US (2) US6642558B1 (en)
EP (1) EP1186050B1 (en)
JP (1) JP2003528470A (en)
AT (1) ATE472174T1 (en)
DE (1) DE60142424D1 (en)
WO (1) WO2001071810A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017105414A1 (en) * 2015-12-15 2017-06-22 General Electric Company Edge termination designs for silicon carbide super-junction power devices

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6231825B1 (en) 1999-07-29 2001-05-15 Rohm And Haas Company Production of sodium borohydride from sodium borohydride dihydrate in a fluidized bed dryer
GB2373634B (en) * 2000-10-31 2004-12-08 Fuji Electric Co Ltd Semiconductor device
US7037814B1 (en) * 2003-10-10 2006-05-02 National Semiconductor Corporation Single mask control of doping levels
WO2006098728A2 (en) * 2005-03-11 2006-09-21 Amerisource Companies, Lp Method and system for item delivery
US9679602B2 (en) 2006-06-14 2017-06-13 Seagate Technology Llc Disc drive circuitry swap
US9305590B2 (en) 2007-10-16 2016-04-05 Seagate Technology Llc Prevent data storage device circuitry swap
US8101997B2 (en) 2008-04-29 2012-01-24 Infineon Technologies Austria Ag Semiconductor device with a charge carrier compensation structure in a semiconductor body and method for its production
US8154078B2 (en) * 2010-02-17 2012-04-10 Vanguard International Semiconductor Corporation Semiconductor structure and fabrication method thereof
US9306034B2 (en) * 2014-02-24 2016-04-05 Vanguard International Semiconductor Corporation Method and apparatus for power device with multiple doped regions
DE102015208097B4 (en) * 2015-04-30 2022-03-31 Infineon Technologies Ag Manufacturing a semiconductor device by epitaxy

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037632A (en) 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1558506A (en) * 1976-08-09 1980-01-03 Mullard Ltd Semiconductor devices having a rectifying metalto-semicondductor junction
GB2089119A (en) 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
GB2104287B (en) * 1981-08-21 1985-02-20 Gen Electric Co Plc Data storage devices
GB2131603B (en) * 1982-12-03 1985-12-18 Philips Electronic Associated Semiconductor devices
DE3581348D1 (en) * 1984-09-28 1991-02-21 Siemens Ag METHOD FOR PRODUCING A PN TRANSITION WITH A HIGH BREAKTHROUGH VOLTAGE.
JPH0644578B2 (en) * 1984-12-21 1994-06-08 三菱電機株式会社 Charge transfer device
US4648174A (en) * 1985-02-05 1987-03-10 General Electric Company Method of making high breakdown voltage semiconductor device
DE3715675A1 (en) * 1987-05-11 1988-12-01 Messerschmitt Boelkow Blohm SEMICONDUCTOR ELEMENT
US4927772A (en) * 1989-05-30 1990-05-22 General Electric Company Method of making high breakdown voltage semiconductor device
DE69209678T2 (en) * 1991-02-01 1996-10-10 Philips Electronics Nv Semiconductor device for high voltage use and manufacturing method
JP3192809B2 (en) * 1993-03-12 2001-07-30 株式会社東芝 High pressure silicon carbide Schottky diode
EP0661753A1 (en) * 1994-01-04 1995-07-05 Motorola, Inc. Semiconductor structure with field limiting ring and method for making
US5486718A (en) * 1994-07-05 1996-01-23 Motorola, Inc. High voltage planar edge termination structure and method of making same
DE69525003T2 (en) * 1994-08-15 2003-10-09 Siliconix Inc., Santa Clara Method of manufacturing a trench-structure DMOS transistor using seven masks
US5967795A (en) * 1995-08-30 1999-10-19 Asea Brown Boveri Ab SiC semiconductor device comprising a pn junction with a voltage absorbing edge
KR970024275A (en) * 1995-10-10 1997-05-30 김광호 Transistor with increased safe operating area and manufacturing method thereof
US5940721A (en) * 1995-10-11 1999-08-17 International Rectifier Corporation Termination structure for semiconductor devices and process for manufacture thereof
DE59707158D1 (en) 1996-02-05 2002-06-06 Infineon Technologies Ag CONTROLLABLE SEMICONDUCTOR COMPONENT THROUGH FIELD EFFECT
JPH09268202A (en) * 1996-03-29 1997-10-14 Mitsubishi Rayon Co Ltd Syrup and production of the same
US6002159A (en) * 1996-07-16 1999-12-14 Abb Research Ltd. SiC semiconductor device comprising a pn junction with a voltage absorbing edge
JP3632344B2 (en) * 1997-01-06 2005-03-23 日産自動車株式会社 Semiconductor device
SE9700156D0 (en) * 1997-01-21 1997-01-21 Abb Research Ltd Junction termination for Si C Schottky diode
US5932894A (en) * 1997-06-26 1999-08-03 Abb Research Ltd. SiC semiconductor device comprising a pn junction
US6870201B1 (en) 1997-11-03 2005-03-22 Infineon Technologies Ag High voltage resistant edge structure for semiconductor components
SE512259C2 (en) * 1998-03-23 2000-02-21 Abb Research Ltd Semiconductor device consisting of doped silicon carbide comprising a pn junction which exhibits at least one hollow defect and method for its preparation
WO1999053550A1 (en) 1998-04-08 1999-10-21 Siemens Aktiengesellschaft High-voltage edge termination for planar structures
DE19816448C1 (en) * 1998-04-14 1999-09-30 Siemens Ag Universal semiconductor wafer for high-voltage semiconductor components, their manufacturing process and their use
US6096663A (en) * 1998-07-20 2000-08-01 Philips Electronics North America Corporation Method of forming a laterally-varying charge profile in silicon carbide substrate
US6355508B1 (en) * 1998-09-02 2002-03-12 Micron Technology, Inc. Method for forming electrostatic discharge protection device having a graded junction
DE19843659A1 (en) * 1998-09-23 2000-04-06 Siemens Ag Semiconductor component with a structured semiconductor body
DE69833743T2 (en) * 1998-12-09 2006-11-09 Stmicroelectronics S.R.L., Agrate Brianza Manufacturing method of an integrated edge structure for high voltage semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037632A (en) 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017105414A1 (en) * 2015-12-15 2017-06-22 General Electric Company Edge termination designs for silicon carbide super-junction power devices

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US6927103B2 (en) 2005-08-09
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DE60142424D1 (en) 2010-08-05
EP1186050A1 (en) 2002-03-13
US6642558B1 (en) 2003-11-04
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US20040104430A1 (en) 2004-06-03

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