DE60139695D1 - Eine kupfer-verbindungsstruktur mit verbesserter zwischenfläche und haftung - Google Patents

Eine kupfer-verbindungsstruktur mit verbesserter zwischenfläche und haftung

Info

Publication number
DE60139695D1
DE60139695D1 DE60139695T DE60139695T DE60139695D1 DE 60139695 D1 DE60139695 D1 DE 60139695D1 DE 60139695 T DE60139695 T DE 60139695T DE 60139695 T DE60139695 T DE 60139695T DE 60139695 D1 DE60139695 D1 DE 60139695D1
Authority
DE
Germany
Prior art keywords
interiors
liability
connection structure
copper connection
improved intermediate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60139695T
Other languages
English (en)
Inventor
Minh Van Ngo
Hartmut Ruelke
Lothar Mergili
Joerg Hohage
Lu You
Robert A Huertas
Richard Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE60139695D1 publication Critical patent/DE60139695D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/913—Diverse treatments performed in unitary chamber

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
DE60139695T 2000-07-26 2001-06-04 Eine kupfer-verbindungsstruktur mit verbesserter zwischenfläche und haftung Expired - Lifetime DE60139695D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/626,455 US6596631B1 (en) 2000-07-26 2000-07-26 Method of forming copper interconnect capping layers with improved interface and adhesion
PCT/US2001/018228 WO2002009173A2 (en) 2000-07-26 2001-06-04 Method of forming copper interconnect capping layers with improved interface and adhesion

Publications (1)

Publication Number Publication Date
DE60139695D1 true DE60139695D1 (de) 2009-10-08

Family

ID=24510446

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60139695T Expired - Lifetime DE60139695D1 (de) 2000-07-26 2001-06-04 Eine kupfer-verbindungsstruktur mit verbesserter zwischenfläche und haftung

Country Status (9)

Country Link
US (1) US6596631B1 (de)
EP (1) EP1303876B1 (de)
JP (1) JP2004505447A (de)
KR (1) KR100774599B1 (de)
CN (1) CN1276498C (de)
AU (1) AU2001275273A1 (de)
DE (1) DE60139695D1 (de)
TW (1) TW512491B (de)
WO (1) WO2002009173A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3705724B2 (ja) * 1999-11-19 2005-10-12 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
DE10059143B4 (de) * 2000-11-29 2006-12-28 Advanced Micro Devices, Inc., Sunnyvale Oberflächenbehandlungs- und Deckschichtverfahren zur Herstellung einer Kupfergrenzfläche in einem Halbleiterbauteil
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
DE10150822B4 (de) * 2001-10-15 2007-01-25 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Entfernen oxidierter Bereiche auf einer Grenzfläche einer Metalloberfläche
US6977218B2 (en) * 2003-07-17 2005-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating copper interconnects
KR101044611B1 (ko) * 2004-06-25 2011-06-29 매그나칩 반도체 유한회사 반도체 소자의 금속 배선 형성 방법
JP4516447B2 (ja) 2005-02-24 2010-08-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7534732B1 (en) 2006-02-17 2009-05-19 Spansion Llc Semiconductor devices with copper interconnects and composite silicon nitride capping layers
US7713866B2 (en) * 2006-11-21 2010-05-11 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
JP2009141058A (ja) 2007-12-05 2009-06-25 Fujitsu Microelectronics Ltd 半導体装置およびその製造方法
CN102263056A (zh) * 2010-05-26 2011-11-30 中芯国际集成电路制造(上海)有限公司 一种金属互连方法
CN102446833B (zh) * 2011-09-29 2015-04-29 上海华力微电子有限公司 一种降低双大马士革氮化硅工艺颗粒的处理方法
US9269612B2 (en) * 2011-11-22 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of forming damascene interconnect structures
WO2014021777A1 (en) * 2012-07-31 2014-02-06 Nanyang Technological University Semiconductor device and method for forming the same
CN104157603B (zh) * 2013-05-15 2017-02-08 中芯国际集成电路制造(上海)有限公司 一种增强金属铜与ndc界面结合强度的方法
JP2020043263A (ja) * 2018-09-12 2020-03-19 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174810B1 (en) * 1998-04-06 2001-01-16 Motorola, Inc. Copper interconnect structure and method of formation
US6242347B1 (en) * 1998-09-30 2001-06-05 Applied Materials, Inc. Method for cleaning a process chamber
US20010049181A1 (en) * 1998-11-17 2001-12-06 Sudha Rathi Plasma treatment for cooper oxide reduction
US6153523A (en) * 1998-12-09 2000-11-28 Advanced Micro Devices, Inc. Method of forming high density capping layers for copper interconnects with improved adhesion
US6225210B1 (en) * 1998-12-09 2001-05-01 Advanced Micro Devices, Inc. High density capping layers with improved adhesion to copper interconnects
US6271595B1 (en) * 1999-01-14 2001-08-07 International Business Machines Corporation Method for improving adhesion to copper

Also Published As

Publication number Publication date
AU2001275273A1 (en) 2002-02-05
KR100774599B1 (ko) 2007-11-09
EP1303876B1 (de) 2009-08-26
JP2004505447A (ja) 2004-02-19
WO2002009173A3 (en) 2002-05-23
US6596631B1 (en) 2003-07-22
KR20030020415A (ko) 2003-03-08
TW512491B (en) 2002-12-01
CN1276498C (zh) 2006-09-20
CN1552096A (zh) 2004-12-01
WO2002009173A2 (en) 2002-01-31
EP1303876A2 (de) 2003-04-23

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Legal Events

Date Code Title Description
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