DE60103222D1 - Gerät und Verfahren für eine Hauptrechnersportschnitstelleneinheit in einer Einrichtung zur digitalen Signalverarbeitung - Google Patents

Gerät und Verfahren für eine Hauptrechnersportschnitstelleneinheit in einer Einrichtung zur digitalen Signalverarbeitung

Info

Publication number
DE60103222D1
DE60103222D1 DE60103222T DE60103222T DE60103222D1 DE 60103222 D1 DE60103222 D1 DE 60103222D1 DE 60103222 T DE60103222 T DE 60103222T DE 60103222 T DE60103222 T DE 60103222T DE 60103222 D1 DE60103222 D1 DE 60103222D1
Authority
DE
Germany
Prior art keywords
interface unit
unit
host port
port interface
signal groups
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60103222T
Other languages
English (en)
Other versions
DE60103222T2 (de
Inventor
Patrick J Smith
Jason A Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE60103222D1 publication Critical patent/DE60103222D1/de
Publication of DE60103222T2 publication Critical patent/DE60103222T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
DE60103222T 2000-09-27 2001-09-26 Gerät und Verfahren für eine Hauptrechnersportschnitstelleneinheit in einer Einrichtung zur digitalen Signalverarbeitung Expired - Lifetime DE60103222T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67066500A 2000-09-27 2000-09-27
US670665 2000-09-27

Publications (2)

Publication Number Publication Date
DE60103222D1 true DE60103222D1 (de) 2004-06-17
DE60103222T2 DE60103222T2 (de) 2005-05-04

Family

ID=24691340

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60103222T Expired - Lifetime DE60103222T2 (de) 2000-09-27 2001-09-26 Gerät und Verfahren für eine Hauptrechnersportschnitstelleneinheit in einer Einrichtung zur digitalen Signalverarbeitung

Country Status (4)

Country Link
EP (1) EP1193606B1 (de)
JP (1) JP2002157213A (de)
AT (1) ATE266883T1 (de)
DE (1) DE60103222T2 (de)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182800A (en) * 1990-11-16 1993-01-26 International Business Machines Corporation Direct memory access controller with adaptive pipelining and bus control features
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes

Also Published As

Publication number Publication date
DE60103222T2 (de) 2005-05-04
EP1193606B1 (de) 2004-05-12
ATE266883T1 (de) 2004-05-15
EP1193606A3 (de) 2002-08-28
EP1193606A2 (de) 2002-04-03
JP2002157213A (ja) 2002-05-31

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Legal Events

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8364 No opposition during term of opposition