ATE266883T1 - Gerät und verfahren für eine hauptrechnersportschnitstelleneinheit in einer einrichtung zur digitalen signalverarbeitung - Google Patents
Gerät und verfahren für eine hauptrechnersportschnitstelleneinheit in einer einrichtung zur digitalen signalverarbeitungInfo
- Publication number
- ATE266883T1 ATE266883T1 AT01000501T AT01000501T ATE266883T1 AT E266883 T1 ATE266883 T1 AT E266883T1 AT 01000501 T AT01000501 T AT 01000501T AT 01000501 T AT01000501 T AT 01000501T AT E266883 T1 ATE266883 T1 AT E266883T1
- Authority
- AT
- Austria
- Prior art keywords
- interface unit
- unit
- host port
- port interface
- signal groups
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Selective Calling Equipment (AREA)
- Image Input (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US67066500A | 2000-09-27 | 2000-09-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE266883T1 true ATE266883T1 (de) | 2004-05-15 |
Family
ID=24691340
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT01000501T ATE266883T1 (de) | 2000-09-27 | 2001-09-26 | Gerät und verfahren für eine hauptrechnersportschnitstelleneinheit in einer einrichtung zur digitalen signalverarbeitung |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1193606B1 (de) |
JP (1) | JP2002157213A (de) |
AT (1) | ATE266883T1 (de) |
DE (1) | DE60103222T2 (de) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5182800A (en) * | 1990-11-16 | 1993-01-26 | International Business Machines Corporation | Direct memory access controller with adaptive pipelining and bus control features |
US5535417A (en) * | 1993-09-27 | 1996-07-09 | Hitachi America, Inc. | On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes |
-
2001
- 2001-09-26 AT AT01000501T patent/ATE266883T1/de not_active IP Right Cessation
- 2001-09-26 EP EP01000501A patent/EP1193606B1/de not_active Expired - Lifetime
- 2001-09-26 DE DE60103222T patent/DE60103222T2/de not_active Expired - Lifetime
- 2001-09-26 JP JP2001293784A patent/JP2002157213A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP1193606A2 (de) | 2002-04-03 |
EP1193606A3 (de) | 2002-08-28 |
JP2002157213A (ja) | 2002-05-31 |
DE60103222T2 (de) | 2005-05-04 |
EP1193606B1 (de) | 2004-05-12 |
DE60103222D1 (de) | 2004-06-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69228521D1 (de) | Mikroprozessorarchitektur mit der möglichkeit zur unterstützung mehrerer verschiedener prozessoren | |
CA2245106A1 (en) | Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access | |
JPH0137773B2 (de) | ||
DE60044695D1 (de) | Cachespeicher und System | |
ATE363690T1 (de) | Methode und vorrichtung welche einen externen zugriff zu internen konfigurationsregistern erlauben | |
KR950008229B1 (ko) | 퍼스널 컴퓨터 시스템 | |
DE60103222D1 (de) | Gerät und Verfahren für eine Hauptrechnersportschnitstelleneinheit in einer Einrichtung zur digitalen Signalverarbeitung | |
JPS62239235A (ja) | オペレ−シヨンコ−ドの高速比較動作を備えたデ−タプロセツサ | |
JPS59183424A (ja) | 情報処理装置 | |
JP3207329B2 (ja) | バスコントローラおよびバス転送方法 | |
TW480404B (en) | Memory card with signal processing element | |
JPH03271859A (ja) | 情報処理装置 | |
JPS642985B2 (de) | ||
JPS62171065A (ja) | デ−タ転送方式 | |
JP2004280677A (ja) | バス制御装置及びそのデータアクセス制御方法 | |
JPH0612363A (ja) | メモリ制御装置およびマルチプロセッサシステム | |
JPH1040213A (ja) | 情報処理装置のdmaデータ転送方法 | |
JPH0449446A (ja) | 複数キャッシュ制御方式 | |
JPS62204363A (ja) | 共有メモリ方式 | |
JPH04337851A (ja) | メモリアクセス方式 | |
JPH0784871A (ja) | 連続アドレスデータ用メモリのアクセス回路 | |
JPH06259372A (ja) | Dmaコントローラ周辺回路 | |
JPS60195660A (ja) | Dma制御回路方式 | |
JPH02123450A (ja) | 情報処理システム | |
JPH04117538A (ja) | メモリ制御方式 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |