DE60032497D1 - Verfahren und anordnung zur leistungsversorgung von geregelter speisespannungfür speicherkomponenten - Google Patents

Verfahren und anordnung zur leistungsversorgung von geregelter speisespannungfür speicherkomponenten

Info

Publication number
DE60032497D1
DE60032497D1 DE60032497T DE60032497T DE60032497D1 DE 60032497 D1 DE60032497 D1 DE 60032497D1 DE 60032497 T DE60032497 T DE 60032497T DE 60032497 T DE60032497 T DE 60032497T DE 60032497 D1 DE60032497 D1 DE 60032497D1
Authority
DE
Germany
Prior art keywords
regulator
voltage
arrays
charge pumps
output voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60032497T
Other languages
English (en)
Other versions
DE60032497T2 (de
Inventor
W Butler
L Casper
R Porter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE60032497D1 publication Critical patent/DE60032497D1/de
Application granted granted Critical
Publication of DE60032497T2 publication Critical patent/DE60032497T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Dc-Dc Converters (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60032497T 1999-09-01 2000-08-31 Verfahren und anordnung zur leistungsversorgung von geregelter speisespannung für speicherkomponenten Expired - Lifetime DE60032497T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US388126 1989-07-31
US09/388,126 US6219293B1 (en) 1999-09-01 1999-09-01 Method and apparatus for supplying regulated power to memory device components
PCT/US2000/024346 WO2001016956A1 (en) 1999-09-01 2000-08-31 Method and apparatus for supplying regulated power to memory device components

Publications (2)

Publication Number Publication Date
DE60032497D1 true DE60032497D1 (de) 2007-02-01
DE60032497T2 DE60032497T2 (de) 2007-10-04

Family

ID=23532816

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60032497T Expired - Lifetime DE60032497T2 (de) 1999-09-01 2000-08-31 Verfahren und anordnung zur leistungsversorgung von geregelter speisespannung für speicherkomponenten

Country Status (8)

Country Link
US (2) US6219293B1 (de)
EP (1) EP1218887B1 (de)
JP (1) JP2003508871A (de)
KR (1) KR100738828B1 (de)
AT (1) ATE349059T1 (de)
AU (1) AU7114700A (de)
DE (1) DE60032497T2 (de)
WO (1) WO2001016956A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650589B2 (en) * 2001-11-29 2003-11-18 Intel Corporation Low voltage operation of static random access memory
US6785161B2 (en) 2002-06-28 2004-08-31 Micron Technology, Inc. High voltage regulator for low voltage integrated circuit processes
KR100460459B1 (ko) * 2002-07-30 2004-12-08 삼성전자주식회사 향상된 테스트 모드를 갖는 반도체 메모리 장치
US6859408B2 (en) * 2002-08-29 2005-02-22 Micron Technology, Inc. Current limiting antifuse programming path
ITRM20030338A1 (it) * 2003-07-11 2005-01-12 Micron Technology Inc Circuito di generazione e regolazione di alta tensione
TWM241879U (en) * 2003-09-08 2004-08-21 Well Shin Technology Co Ltd Multi-functional adapter
US20050138497A1 (en) * 2003-12-19 2005-06-23 Hassan Mohamed A. Apparatus and method for testing a flash memory unit
US20050149785A1 (en) * 2003-12-19 2005-07-07 Hassan Mohamed A. Apparatus and method for testing a flash memory unit using stress voltages
US6992939B2 (en) * 2004-01-26 2006-01-31 Micron Technology, Inc. Method and apparatus for identifying short circuits in an integrated circuit device
US7702479B2 (en) * 2005-05-12 2010-04-20 International Business Machines Corporation On-board guard-band chamber environment emulator
JP2007133996A (ja) * 2005-11-11 2007-05-31 Toshiba Corp 半導体記憶装置及びその制御方法
KR100872165B1 (ko) * 2006-12-28 2008-12-09 삼성전자주식회사 저항체를 이용한 비휘발성 메모리 장치
KR102171261B1 (ko) * 2013-12-27 2020-10-28 삼성전자 주식회사 다수의 전압 발생부들을 갖는 메모리 장치
US10453539B2 (en) * 2017-01-03 2019-10-22 Samsung Electronics Co., Ltd. Device for detecting leakage current and memory device
US11948625B2 (en) * 2021-09-09 2024-04-02 Winbond Electronics Corporation Systems on chips, memory circuits, and methods for accessing data in a memory circuit directly using a transistor-level operation signal
US11955196B2 (en) * 2022-07-13 2024-04-09 Nanya Technology Corporation Memory device, voltage generating device and voltage generating method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446367A (en) * 1993-05-25 1995-08-29 Micron Semiconductor, Inc. Reducing current supplied to an integrated circuit
US5552739A (en) * 1994-02-08 1996-09-03 Micron Technology, Inc. Integrated circuit power supply having piecewise linearity
JP3155879B2 (ja) * 1994-02-25 2001-04-16 株式会社東芝 半導体集積回路装置
US5596534A (en) * 1995-06-27 1997-01-21 Micron Technology, Inc. Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM

Also Published As

Publication number Publication date
KR20020043572A (ko) 2002-06-10
US20010012220A1 (en) 2001-08-09
ATE349059T1 (de) 2007-01-15
US6385098B2 (en) 2002-05-07
EP1218887B1 (de) 2006-12-20
WO2001016956A1 (en) 2001-03-08
JP2003508871A (ja) 2003-03-04
US6219293B1 (en) 2001-04-17
DE60032497T2 (de) 2007-10-04
KR100738828B1 (ko) 2007-07-13
AU7114700A (en) 2001-03-26
EP1218887A1 (de) 2002-07-03
EP1218887A4 (de) 2004-10-13

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Legal Events

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