US20010012220A1 - Method and apparatus for supplying regulated power to memory device components - Google Patents
Method and apparatus for supplying regulated power to memory device components Download PDFInfo
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- US20010012220A1 US20010012220A1 US09/836,947 US83694701A US2001012220A1 US 20010012220 A1 US20010012220 A1 US 20010012220A1 US 83694701 A US83694701 A US 83694701A US 2001012220 A1 US2001012220 A1 US 2001012220A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Definitions
- This invention relates to memory devices, and more particularly, to a method and apparatus for supplying regulated power to various components of memory devices in a manner that facilitates stress testing of the components.
- Memory devices are in common use in a wide variety of applications. For example, memory devices are used in personal computers, telephone answering machines, and cellular telephones. Various types of memory devices are commercially available, including read-only memories (“ROMs”), which may be programmable (“PROMs”), and random access memories (“RAMs”), which may be either static random access memories (“SRAMs”) or dynamic random access memories (“DRAMs”). Furthermore, there are a variety of DRAM types available, and more being developed. For example, asynchronous DRAMs, synchronous DRAMs (“SDRAMs”), and video graphics DRAMs are currently available, and Synchronous Link DRAMs (“SLDRAMs”) and RAMBUS DRAMs (“RDRAMs”) will soon be available.
- ROMs read-only memories
- PROMs programmable
- RAMs random access memories
- SRAMs static random access memories
- DRAMs dynamic random access memories
- DRAMs dynamic random access memories
- FIG. 1 One example of a conventional SDRAM 10 exhibiting problems that can be alleviated using the disclosed embodiments of the invention is shown in FIG. 1.
- the SDRAM 10 includes an address register 12 that receives either a row address or a column address on an address bus 14 .
- the address bus 14 is generally coupled to a memory controller (not shown in FIG. 1).
- a row address is initially received by the address register 12 and applied to a row address multiplexer 18 .
- the row address multiplexer 18 couples the row address to a number of components associated with either of two memory banks 20 , 22 depending upon the state of a bank address bit BA forming part of the row address.
- each of the memory banks 20 , 22 Associated with each of the memory banks 20 , 22 are a respective row address latch 30 which, stores the row address, and a row decoder 32 , which applies various row signals to its respective array 20 or 22 as a function of the stored row address.
- the row address multiplexer 18 also couples row addresses to the row address latches 30 for the purpose of refreshing the memory cells in the arrays 20 , 22 .
- the row addresses are generated for refresh purposes by a refresh counter 40 , which is controlled by a refresh controller 42 .
- a column address is applied to the address register 12 .
- the address register 12 couples the column address to a column address latch 50 .
- the column address is either coupled through a burst counter 52 to a column address buffer 56 or to the burst counter 52 which applies a sequence of column addresses to the column address buffer 56 starting at the column address output by the address register 12 .
- the column address buffer 56 applies a column address to a column decoder 58 , which applies various column signals to respective column circuitry 60 , 62 , each of which includes sense amplifiers and associated circuitry.
- the column circuitry 60 , 62 receive data from the arrays 20 , 22 , respectively, and couple the data to a data output register 70 , which applies the data to a data bus 72 .
- Data to be written to one of the arrays 20 , 22 is coupled from the data bus 72 through a data input register 74 to the column circuitry 60 , 62 where it is transferred to one of the arrays 20 , 22 , respectively.
- a mask register 76 may be used to selectively alter the flow of data into and out of the column circuitry 60 , 62 such as by selectively masking data to be read from the arrays 20 , 22 , respectively.
- the above-described operation of the SDRAM 10 is controlled by a command decoder 78 responsive to high level command signals received on a control bus 79 .
- These high level command signals which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low.
- the command decoder 78 generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals.
- the SDRAM 10 also includes an internal voltage regulator 80 that supplies various regulated voltages, including V PP , V CCR1 and V CCR2 .
- V PP is typically a “pumped” voltage having a magnitude greater than the magnitude of an external supply voltage V CCX , and is used for such purposes as generating wordline voltages for the arrays 20 , 22 , and supplying power to the data output register 70 .
- a negative pumped voltage V BB may also be generated that is used to bias the substrate of the SDRAM 10 .
- the voltage V CCR1 is typically a regulated voltage that is used to apply power to the arrays 20 , 22
- V CCR2 is typically a regulated voltage that is used to apply power to the other circuitry in the SDRAM 10 .
- the internal voltage regulator 80 is illustrated in further detail in FIG. 2.
- the voltage regulator 80 includes three internal voltage regulator circuits 90 , 92 , 94 , each of which is powered by the external power supply voltage V CCX .
- the voltage regulator circuits 90 , 92 , 94 are identical to each other, and thus have the same performance characteristics.
- Each of the voltage regulator circuits 90 , 92 , 94 is also coupled to a reference voltage generator 96 , which supplies the voltage regulator circuits 90 , 92 , 94 with a common reference voltage V REF .
- the design of the reference voltage circuit 96 which has the characteristics described below, is well within the ability of one of ordinary skill in the art. Therefore, in the interests of brevity, a specific design for the reference voltage circuit 96 will not be described.
- the voltage regulator circuit 90 generates a regulated voltage V CCR1 which, as explained above, supplies power to the arrays 20 , 22 .
- the voltage regulator circuit 92 generates a regulated voltage V CCR2 which supplies power to the other circuitry in the SDRAM 10 .
- the voltage regulator circuit 94 generates a regulated voltage V CCR3 , which supplies power to conventional charge pumps 98 .
- the charge pumps 98 which are generally entirely separate circuits (not shown) for each pumped supply voltage, generate a positive pumped supply voltage V PP , which may be used as described above, and a negative voltage V BB , which, as described above, is used to bias the substrate of the SDRAM 10 .
- FIG. 3 The performance characteristic of the regulator circuits 90 , 92 , 94 is shown in FIG. 3, in which the regulated output voltage V CCR is shown on the y-axis as a function of the external supply voltage V CCX plotted on the x-axis.
- the regulated output voltage V CCR increases linearly with the external supply voltage V CCX until the regulator circuits 90 , 92 , 94 begin to regulate, which occurs at about two volts. Thereafter, the regulated output voltage V CCR remains constant as the external supply voltage V CCX continues to increase.
- the regulator circuits 90 , 92 , 94 are only capable of regulating the output voltage V CCR over a limited range of supply voltages.
- the output voltage from the regulator circuits 90 , 92 , 94 starts to increase linearly with V CCX in order to perform stress testing. Also, even if the regulator circuits 90 , 92 , 94 are capable of regulating when the external supply voltage V CCX is above 4 volts, they may still perform as illustrated in FIG. 3 if the reference voltage V REF increases with the external supply voltage V CCX when the external supply voltage V CCX is above 4 volts.
- the performance characteristics of the regulator circuits 90 , 92 , 94 do not present a problem during normal operation of the SDRAM 10 because the external supply voltage V CCX is normally maintained within the operating range of the regulator circuits 90 , 92 , 94 . However, these performance characteristics do present a problem during testing of the SDRAM 10 , as explained below.
- the other regulated output voltages V CCR1 and V CCR2 are normally proportional to the external supply voltage V CCX above the normal operating range of the regulator circuits 90 , 92 , 94 , the voltages present in the circuitry powered by the output voltages V CCR1 and V CCR2 are relatively low since V CCR1 and V CCR2 are typically less than V CCX .
- the external supply voltage V CCX is increased above the normal operating range of the regulator circuits 90 , 92 , 94 , the resulting high voltages present in the charge pumps 98 , which may be 2-3 times the magnitude of the supply voltage, can damage the charge pumps 98 , even though the arrays 20 , 22 and other circuitry in the SDRAM 10 would continue to operate.
- the performance characteristics of the regulator circuits 90 , 92 , 94 it can be impractical to stress test the SDRAM 10 at adequately high external supply voltages V CCX .
- the regulator circuits 90 , 92 , 94 have been described as generating output voltages V CCR1 , V CCR2 and V CCR2 having the same magnitude. However, it will be understood that the problems described above would continue to exist even if the regulator circuits 90 , 92 , 94 were adjusted to output regulated output voltages V CCR1 , V CCR2 and V CCR3 having different magnitudes or some of the regulated output voltages V CCR1 , V CCR2 and V CCR3 were scaled to a lower voltage.
- the regulator circuit 90 generates an output voltage V CCR1 of 1.5 volts and the regulator circuit 94 generates an output voltage V CCR3 of 3 volts when an external supply voltage V CCX within the normal operating range of the regulator circuits 90 , 92 , 94 is applied to the SDRAM 10
- the regulator circuit 90 would generate an output voltage V CCR1 of 2.5 volts and the regulator circuit 94 would generate an output voltage V CCR3 of 4 volts.
- This regulated voltage V CCR3 of 4 volts might very well damage the charge pumps 98 even though the arrays 20 , 22 would continue to operate without damage at a regulated output voltage V CCR1 of 2.5 volts.
- an internal voltage regulator provides power to a memory device having an array of memory cells and a charge pump.
- the internal voltage regulator includes at least two regulator circuits adapted to receive an external supply voltage and operable to generate respective regulated output voltages.
- the first regulator circuit supplies a first regulated output voltage to the array of memory cells, and the second regulator circuit supplies a second regulated output voltage to the charge pump.
- the first regulator circuit generates the first regulated output voltage as a first function of the external supply voltage
- the second regulator circuit generates the second regulated output voltage as a second function of the external supply voltage, the second function being different from the first function.
- the first regulator circuit supplies power to at least a portion of the array at a first voltage when the external supply voltage has a magnitude that is less than a predetermined voltage.
- the first regulator circuit supplies power to the array at a voltage having a magnitude that is greater than the magnitude of the first voltage.
- the second voltage regulator supplies power to the charge pump at a second voltage when the external supply voltage has a magnitude that is less than the predetermined voltage and also when the external supply voltage has a magnitude that is greater than the predetermined voltage.
- FIG. 1 is a block diagram of a conventional memory device.
- FIG. 2 is a block diagram of a conventional system for supplying regulated power to various components in the memory device of FIG. 1.
- FIG. 3 is a graph showing the voltage generated by the system of FIG. 2 as a function of reference voltage or input power voltage.
- FIG. 4 is a block diagram of one embodiment of the invention for supplying regulated power to various components in the memory device of FIG. 1.
- FIGS. 5A and 5B are graphs showing the voltage generated by the embodiment of the invention shown in FIG. 4 as a function of the external supply voltage.
- FIG. 6 is a block diagram of another embodiment of the invention for supplying regulated power to various components in the memory device of FIG. 1.
- FIG. 7 is a block diagram of a computer system that includes the memory device of FIG. 1 containing an embodiment of the inventive system for supplying regulated power to components in the memory device.
- FIG. 4 One embodiment of an internal voltage regulator 80 ′ in accordance with the invention is illustrated in FIG. 4.
- the voltage regulator 80 ′ may be used in the SDRAM 10 (FIG. 1) in place of the voltage regulator 80 .
- the voltage regulator 80 ′ like the voltage regulator 80 , includes three identical voltage regulator circuits 100 , 102 , 104 .
- the voltage regulator circuit 100 generates a regulated output voltage V CCR1 that supplies power to the arrays 20 , 22 .
- the regulator circuit 102 generates a regulated output voltage V CCR2 that supplies power to the other circuitry in the SDRAM 10 .
- the regulator circuit 104 generates a regulated output voltage V CCR3 that supplies power to the charge pumps 98 .
- the charge pumps 98 then produce a pumped output voltage V PP and a substrate bias voltage V BB .
- the embodiment of the internal voltage regulator 80 ′ shown in FIG. 4 includes a respective reference voltage generator 110 , 112 , 114 for each of the regulator circuits 100 , 102 , 104 .
- the reference voltage generator 110 applies a reference voltage V REF1 to the voltage regulator circuit 100
- the reference voltage generator 112 applies a reference voltage V REF2 to the voltage regulator circuit 102
- the reference voltage generator 114 applies a reference voltage V REF3 to the voltage regulator circuit 104 .
- the reference voltage V REF3 applied to the regulator circuit 104 may be different from the reference voltage V REF1 and V REF2 applied to at least one of the other regulator circuits 100 , 102 . More particularly, since the reference voltage V REF3 applied to the regulator circuit 104 is different, the performance characteristic of the regulator circuit 104 may be different. As mentioned above, the design of the reference voltage circuits 110 , 112 , 114 having the characteristics described herein is well within the ability of those skilled in the art. Therefore, in the interest of brevity, an explanation of specific reference voltage circuits will be omitted.
- the regulator circuit 104 receives a reference voltage V REF3 that increases linearly with the external supply voltage V CCX until the reference voltage V REF3 reaches 1.5 volts.
- the regulated output voltage V CCR3 also increases linearly with the external supply voltage V CCX at twice the rate as the reference voltage V REF3 until the regulated output voltage V CCR3 reaches 3 volts.
- the reference voltage V REF3 then remains constant at 1.5 volts as the external supply voltage V CCX continues to increase.
- the constant value of the reference voltage V REF3 causes the regulated output voltage V CCR3 to likewise remain constant at 3 volts.
- the regulated output voltage V CCR3 remains at 3 volts, thereby preventing an excessive voltage from being applied to the charge pumps 98 .
- the regulator circuit 100 supplying power to the arrays 20 , 22 operates in a manner that is similar to that of regulator circuit 104 as the external supply voltage V CCX is initially increased.
- the reference voltage V REF1 no longer increases with the external supply voltage V CCX when the reference voltage V REF1 reaches 1.25 volts.
- the regulated output voltage V CCR1 no longer increases linearly with the external supply voltage V CCX when the regulated output voltage V REF1 reaches 2.5 volts.
- the reference voltage V REF1 and the regulated output voltage V CCR1 remain constant until the external supply voltage V CCX reaches 4 volts. Thereafter, the reference voltage V REF1 increases linearly at half the rate of the external supply voltage V CCX .
- the regulated output voltage V CCR1 increases linearly with the external supply voltage V CCX when the external supply voltage V CCX is increased above 4 volts.
- the regulator circuit 100 applies a regulated output voltage V CCR1 to than the arrays 20 , 22 that increases from 2.5 volts to 3.5 volts as the external supply voltage V CCX increases from its normal operating range to 5 volts.
- the internal voltage regulator 80 ′ is able to stress the arrays 20 , 22 at a higher voltage than normally used without applying excessive voltages to the charge pumps 98 .
- the regulator 80 ′ thus avoids the problems described above with reference to FIGS. 2 and 3 when stress testing the SDRAM 10 with a voltage above the normal range of the external supply voltage V CCX .
- the internal voltage regulator 80 ′ of FIG. 4 uses three separate regulator circuits 100 , 102 , 104 , it will be understood that a fewer or greater number of regulator circuits may be used as long as a separate regulator circuit is provided to power the charge pumps 98 generating the pumped voltage V PP .
- the regulator circuit 104 may supply power to the charge pumps 98
- the regulator circuit 100 may supply power to the arrays 20 , 22 and all of the other circuitry in the SDRAM 10 .
- the regulator circuit 102 would be unnecessary.
- specific performance characteristics of the regulator circuits 100 , 102 , 104 have been described with reference to FIGS. 4 and 5, it will be understood that regulator circuits having other performance characteristics may be used.
- FIG. 6 Another embodiment of a internal voltage regulator in accordance with the invention is illustrated in FIG. 6.
- the internal voltage regulator 80 ′′ has the same topography at conventional voltage regulator 80 of FIG. 2.
- the voltage regulator 80 ′′ uses regulator circuits 120 , 122 , 124 , that, unlike the regulator circuits 90 , 92 , 94 used in the regulator 80 of FIG. 2, are not identical to each other and thus do not have the same performance characteristics.
- the regulator circuit 124 supplying power to charge pumps 98 differs from the regulator circuit 120 supplying power to the arrays 20 , 22 and preferably also to the regulator circuit 122 supplying power to the other circuitry in the SDRAM 10 .
- the regulator circuits 120 , 122 , 124 all receive the same reference voltage V REF from a common reference voltage generator 128 , the performance characteristics of the regulator circuit 124 cause it to generate a regulated output voltage V CCR3 that differs from the regulated output voltage V CCR1 generated by the regulator circuit 120 as the external supply voltage V CCX is increased about its normal operating range.
- the regulator circuit 124 may be designed so that it has the performance characteristics shown in FIG. 5A.
- the regulator circuit 120 may be designed so that it has the performance characteristics shown in FIG. 5B.
- the design of the regulator circuits 120 , 122 , 124 having these characteristics is well within the ability of those skilled in the art. Therefore, in the interest of brevity, an explanation of specific regulator designs will be omitted.
- the voltage regulator 80 ′′ of FIG. 6 may be altered somewhat without departing from the spirit of the invention.
- the regulator circuit 120 may be used to supply power to the arrays 20 , 22 and the other circuitry in the SDRAM 10 , thus making the regulator circuit 122 unnecessary.
- one or more of the regulator circuits 120 , 122 , 124 may include an internal voltage regulating component, such as a zener diode (not shown), thus making the external reference voltage V REF unnecessary.
- FIG. 7 is a block diagram of a computer system 200 that includes the SDRAM 10 of FIG. 1 containing the voltage regulator 80 ′ of FIG. 4 or the voltage regulator 80 ′′ of FIG. 6.
- the computer system 200 includes a processor 202 for performing various computing functions, such as executing specific software to perform specific calculations or tasks.
- the processor 202 includes a processor bus 204 that normally includes an address bus, a control bus, and a data bus.
- the computer system 200 includes one or more input devices 214 , such as a keyboard or a mouse, coupled to the processor 202 to allow an operator to interface with the computer system 200 .
- the computer system 200 also includes one or more output devices 216 coupled to the processor 202 , such output devices typically being a printer or a video terminal.
- One or more data storage devices 218 are also typically coupled to the processor 202 to store data or retrieve data from external storage media (not shown). Examples of typical storage devices 218 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).
- the processor 202 is also typically coupled to cache memory 226 , which is usually static random access memory (“SRAM”) and to the SDRAM 10 through a memory controller 230 .
- the memory controller 230 normally includes the control bus 79 and the address bus 14 that are coupled to the SDRAM 10 .
- the data bus 72 of the SDRAM 10 may be coupled to the processor bus 204 either directly (as shown), through the memory controller 230 , or by some other means.
- voltage regulators in accordance with the invention are capable of supplying regulated power to the internal components of the SDRAM 10 while allowing the arrays to be stress tested with a relatively high voltage without damaging the charge pumps in the SDRAM 10 .
- inventive voltage regulators have been described in the context of an SDRAM 10 , it will be understood that it may be used in other types of memory devices, including DRAMs other than SDRAMs.
Abstract
Description
- This invention relates to memory devices, and more particularly, to a method and apparatus for supplying regulated power to various components of memory devices in a manner that facilitates stress testing of the components.
- Memory devices are in common use in a wide variety of applications. For example, memory devices are used in personal computers, telephone answering machines, and cellular telephones. Various types of memory devices are commercially available, including read-only memories (“ROMs”), which may be programmable (“PROMs”), and random access memories (“RAMs”), which may be either static random access memories (“SRAMs”) or dynamic random access memories (“DRAMs”). Furthermore, there are a variety of DRAM types available, and more being developed. For example, asynchronous DRAMs, synchronous DRAMs (“SDRAMs”), and video graphics DRAMs are currently available, and Synchronous Link DRAMs (“SLDRAMs”) and RAMBUS DRAMs (“RDRAMs”) will soon be available.
- Although the following discussion of problems encountered when testing conventional memory devices will focus on such problems in the context of an SDRAM, it will be understood that these or similar problems exist to varying degrees with other types of memory devices. Similarly, although the solutions to these problems using the disclosed embodiments of the invention are explained in the context of an SDRAM, it will be understood that they are applicable to other types of memory devices.
- One example of a
conventional SDRAM 10 exhibiting problems that can be alleviated using the disclosed embodiments of the invention is shown in FIG. 1. TheSDRAM 10 includes anaddress register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). A row address is initially received by theaddress register 12 and applied to arow address multiplexer 18. Therow address multiplexer 18 couples the row address to a number of components associated with either of twomemory banks memory banks row address latch 30 which, stores the row address, and arow decoder 32, which applies various row signals to itsrespective array row address multiplexer 18 also couples row addresses to therow address latches 30 for the purpose of refreshing the memory cells in thearrays refresh counter 40, which is controlled by arefresh controller 42. - After the row address has been applied to the
address register 12 and stored in one of therow address latches 30, a column address is applied to theaddress register 12. The address register 12 couples the column address to acolumn address latch 50. Depending on the operating mode of theSDRAM 10, the column address is either coupled through aburst counter 52 to acolumn address buffer 56 or to theburst counter 52 which applies a sequence of column addresses to thecolumn address buffer 56 starting at the column address output by theaddress register 12. In either case, thecolumn address buffer 56 applies a column address to acolumn decoder 58, which applies various column signals torespective column circuitry - The
column circuitry arrays data output register 70, which applies the data to adata bus 72. Data to be written to one of thearrays data bus 72 through adata input register 74 to thecolumn circuitry arrays mask register 76 may be used to selectively alter the flow of data into and out of thecolumn circuitry arrays - The above-described operation of the
SDRAM 10 is controlled by acommand decoder 78 responsive to high level command signals received on acontrol bus 79. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low. However, other high level command signals may be used. In either case, thecommand decoder 78 generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. - The
SDRAM 10 also includes aninternal voltage regulator 80 that supplies various regulated voltages, including VPP, VCCR1 and VCCR2. VPP is typically a “pumped” voltage having a magnitude greater than the magnitude of an external supply voltage VCCX, and is used for such purposes as generating wordline voltages for thearrays data output register 70. However, a negative pumped voltage VBB may also be generated that is used to bias the substrate of theSDRAM 10. The voltage VCCR1 is typically a regulated voltage that is used to apply power to thearrays SDRAM 10. - The
internal voltage regulator 80 is illustrated in further detail in FIG. 2. Thevoltage regulator 80 includes three internalvoltage regulator circuits voltage regulator circuits voltage regulator circuits reference voltage generator 96, which supplies thevoltage regulator circuits reference voltage circuit 96, which has the characteristics described below, is well within the ability of one of ordinary skill in the art. Therefore, in the interests of brevity, a specific design for thereference voltage circuit 96 will not be described. - The
voltage regulator circuit 90 generates a regulated voltage VCCR1 which, as explained above, supplies power to thearrays voltage regulator circuit 92 generates a regulated voltage VCCR2 which supplies power to the other circuitry in theSDRAM 10. Finally, thevoltage regulator circuit 94 generates a regulated voltage VCCR3, which supplies power toconventional charge pumps 98. Thecharge pumps 98, which are generally entirely separate circuits (not shown) for each pumped supply voltage, generate a positive pumped supply voltage VPP, which may be used as described above, and a negative voltage VBB, which, as described above, is used to bias the substrate of theSDRAM 10. - The performance characteristic of the
regulator circuits regulator circuits regulator circuits regulator circuits regulator circuits - The performance characteristics of the
regulator circuits SDRAM 10 because the external supply voltage VCCX is normally maintained within the operating range of theregulator circuits SDRAM 10, as explained below. - Difficulties also arise in testing the
SDRAM 10 at external supply voltages VCCX above the normal operating range of theregulator circuits charge pumps 98, the voltages present in thecharge pumps 98 can become very large as the regulated output voltage VCCR3 increases. Although the other regulated output voltages VCCR1 and VCCR2 are normally proportional to the external supply voltage VCCX above the normal operating range of theregulator circuits regulator circuits charge pumps 98, which may be 2-3 times the magnitude of the supply voltage, can damage thecharge pumps 98, even though thearrays SDRAM 10 would continue to operate. As a result of the performance characteristics of theregulator circuits SDRAM 10 at adequately high external supply voltages VCCX. - The
regulator circuits regulator circuits regulator circuit 90 generates an output voltage VCCR1 of 1.5 volts and theregulator circuit 94 generates an output voltage VCCR3 of 3 volts when an external supply voltage VCCX within the normal operating range of theregulator circuits SDRAM 10, When the external supply voltage VCCX is raised 1 volt above the normal operating range, theregulator circuit 90 would generate an output voltage VCCR1 of 2.5 volts and theregulator circuit 94 would generate an output voltage VCCR3 of 4 volts. This regulated voltage VCCR3 of 4 volts might very well damage thecharge pumps 98 even though thearrays - There is therefore a need for an improved method and apparatus for supplying regulated voltages to the components of memory devices, including the
SDRAM 10 and other varieties of DRAMs. - In accordance with one aspect of the invention, an internal voltage regulator provides power to a memory device having an array of memory cells and a charge pump. The internal voltage regulator includes at least two regulator circuits adapted to receive an external supply voltage and operable to generate respective regulated output voltages. The first regulator circuit supplies a first regulated output voltage to the array of memory cells, and the second regulator circuit supplies a second regulated output voltage to the charge pump. The first regulator circuit generates the first regulated output voltage as a first function of the external supply voltage, and the second regulator circuit generates the second regulated output voltage as a second function of the external supply voltage, the second function being different from the first function. In operation, the first regulator circuit supplies power to at least a portion of the array at a first voltage when the external supply voltage has a magnitude that is less than a predetermined voltage. When the external supply voltage has a magnitude that is greater than the predetermined voltage, the first regulator circuit supplies power to the array at a voltage having a magnitude that is greater than the magnitude of the first voltage. In contrast, the second voltage regulator supplies power to the charge pump at a second voltage when the external supply voltage has a magnitude that is less than the predetermined voltage and also when the external supply voltage has a magnitude that is greater than the predetermined voltage. As a result, the voltage of power supplied to the array can be raised by raising the external voltage without raising the voltage of power supplied to the charge pump.
- FIG. 1 is a block diagram of a conventional memory device.
- FIG. 2 is a block diagram of a conventional system for supplying regulated power to various components in the memory device of FIG. 1.
- FIG. 3 is a graph showing the voltage generated by the system of FIG. 2 as a function of reference voltage or input power voltage.
- FIG. 4 is a block diagram of one embodiment of the invention for supplying regulated power to various components in the memory device of FIG. 1.
- FIGS. 5A and 5B are graphs showing the voltage generated by the embodiment of the invention shown in FIG. 4 as a function of the external supply voltage.
- FIG. 6 is a block diagram of another embodiment of the invention for supplying regulated power to various components in the memory device of FIG. 1.
- FIG. 7 is a block diagram of a computer system that includes the memory device of FIG. 1 containing an embodiment of the inventive system for supplying regulated power to components in the memory device.
- One embodiment of an
internal voltage regulator 80′ in accordance with the invention is illustrated in FIG. 4. Thevoltage regulator 80′ may be used in the SDRAM 10 (FIG. 1) in place of thevoltage regulator 80. As shown in FIG. 4, thevoltage regulator 80′, like thevoltage regulator 80, includes three identicalvoltage regulator circuits voltage regulator circuit 100 generates a regulated output voltage VCCR1 that supplies power to thearrays regulator circuit 102 generates a regulated output voltage VCCR2 that supplies power to the other circuitry in theSDRAM 10. Theregulator circuit 104 generates a regulated output voltage VCCR3 that supplies power to the charge pumps 98. The charge pumps 98 then produce a pumped output voltage VPP and a substrate bias voltage VBB. - Unlike the
internal voltage regulator 80 of FIG. 2, the embodiment of theinternal voltage regulator 80′ shown in FIG. 4 includes a respectivereference voltage generator regulator circuits reference voltage generator 110 applies a reference voltage VREF1 to thevoltage regulator circuit 100, thereference voltage generator 112 applies a reference voltage VREF2 to thevoltage regulator circuit 102, and thereference voltage generator 114 applies a reference voltage VREF3 to thevoltage regulator circuit 104. As explained in greater detail below, it is significant that the reference voltage VREF3 applied to theregulator circuit 104 may be different from the reference voltage VREF1 and VREF2 applied to at least one of theother regulator circuits regulator circuit 104 is different, the performance characteristic of theregulator circuit 104 may be different. As mentioned above, the design of thereference voltage circuits - The operation of the
internal voltage regulator 80′ of FIG. 4 will now be explained with reference to FIGS. 5A and 5B. As shown in FIG. 5A, theregulator circuit 104 receives a reference voltage VREF3 that increases linearly with the external supply voltage VCCX until the reference voltage VREF3 reaches 1.5 volts. The regulated output voltage VCCR3 also increases linearly with the external supply voltage VCCX at twice the rate as the reference voltage VREF3 until the regulated output voltage VCCR3 reaches 3 volts. The reference voltage VREF3 then remains constant at 1.5 volts as the external supply voltage VCCX continues to increase. The constant value of the reference voltage VREF3 causes the regulated output voltage VCCR3 to likewise remain constant at 3 volts. As a result, when the external supply voltage VCCX is raised above the normal operating range, e.g. to 5 volts, the regulated output voltage VCCR3 remains at 3 volts, thereby preventing an excessive voltage from being applied to the charge pumps 98. - The
regulator circuit 100 supplying power to thearrays regulator circuit 104 as the external supply voltage VCCX is initially increased. However, the reference voltage VREF1 no longer increases with the external supply voltage VCCX when the reference voltage VREF1 reaches 1.25 volts. Similarly, the regulated output voltage VCCR1 no longer increases linearly with the external supply voltage VCCX when the regulated output voltage VREF1 reaches 2.5 volts. The reference voltage VREF1 and the regulated output voltage VCCR1 remain constant until the external supply voltage VCCX reaches 4 volts. Thereafter, the reference voltage VREF1 increases linearly at half the rate of the external supply voltage VCCX. As a result, the regulated output voltage VCCR1 increases linearly with the external supply voltage VCCX when the external supply voltage VCCX is increased above 4 volts. - The advantages of the
regulator 80′ of FIG. 4 will now be explained using an example in which the external supply voltage VCCX is increased above the normal operating range, e.g. to a voltage of 5 volts. With an external supply voltage VCCX of 5 volts, theregulator circuit 104 continues to apply a regulated output voltage VCCR3 of 3 volts to the charge pumps 98 just as is it did with the external supply voltage VCCX was in its normal operating range, as shown in FIG. 5A. - In contrast, as shown in FIG. 5B, the
regulator circuit 100 applies a regulated output voltage VCCR1 to than thearrays internal voltage regulator 80′ is able to stress thearrays regulator 80′ thus avoids the problems described above with reference to FIGS. 2 and 3 when stress testing theSDRAM 10 with a voltage above the normal range of the external supply voltage VCCX. - Although the
internal voltage regulator 80′ of FIG. 4 uses threeseparate regulator circuits regulator circuit 104 may supply power to the charge pumps 98, and theregulator circuit 100 may supply power to thearrays SDRAM 10. Using this embodiment, theregulator circuit 102 would be unnecessary. Also, although specific performance characteristics of theregulator circuits - Another embodiment of a internal voltage regulator in accordance with the invention is illustrated in FIG. 6. The
internal voltage regulator 80″ has the same topography atconventional voltage regulator 80 of FIG. 2. However, thevoltage regulator 80″ usesregulator circuits regulator circuits regulator 80 of FIG. 2, are not identical to each other and thus do not have the same performance characteristics. Instead, theregulator circuit 124 supplying power to charge pumps 98 differs from theregulator circuit 120 supplying power to thearrays regulator circuit 122 supplying power to the other circuitry in theSDRAM 10. Thus, although theregulator circuits reference voltage generator 128, the performance characteristics of theregulator circuit 124 cause it to generate a regulated output voltage VCCR3 that differs from the regulated output voltage VCCR1 generated by theregulator circuit 120 as the external supply voltage VCCX is increased about its normal operating range. For example, theregulator circuit 124 may be designed so that it has the performance characteristics shown in FIG. 5A. Similarly, theregulator circuit 120 may be designed so that it has the performance characteristics shown in FIG. 5B. The design of theregulator circuits - As with the
internal voltage regulator 80′ of FIG. 4, thevoltage regulator 80″ of FIG. 6 may be altered somewhat without departing from the spirit of the invention. For example, theregulator circuit 120 may be used to supply power to thearrays SDRAM 10, thus making theregulator circuit 122 unnecessary. Also, one or more of theregulator circuits - FIG. 7 is a block diagram of a computer system200 that includes the
SDRAM 10 of FIG. 1 containing thevoltage regulator 80′ of FIG. 4 or thevoltage regulator 80″ of FIG. 6. The computer system 200 includes a processor 202 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 202 includes a processor bus 204 that normally includes an address bus, a control bus, and a data bus. In addition, the computer system 200 includes one or more input devices 214, such as a keyboard or a mouse, coupled to the processor 202 to allow an operator to interface with the computer system 200. Typically, the computer system 200 also includes one or more output devices 216 coupled to the processor 202, such output devices typically being a printer or a video terminal. One or more data storage devices 218 are also typically coupled to the processor 202 to store data or retrieve data from external storage media (not shown). Examples of typical storage devices 218 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor 202 is also typically coupled to cache memory 226, which is usually static random access memory (“SRAM”) and to theSDRAM 10 through a memory controller 230. The memory controller 230 normally includes thecontrol bus 79 and the address bus 14 that are coupled to theSDRAM 10. Thedata bus 72 of theSDRAM 10 may be coupled to the processor bus 204 either directly (as shown), through the memory controller 230, or by some other means. - It is thus seen that voltage regulators in accordance with the invention are capable of supplying regulated power to the internal components of the
SDRAM 10 while allowing the arrays to be stress tested with a relatively high voltage without damaging the charge pumps in theSDRAM 10. As mentioned above, although the inventive voltage regulators have been described in the context of anSDRAM 10, it will be understood that it may be used in other types of memory devices, including DRAMs other than SDRAMs. - From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Claims (33)
Priority Applications (1)
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US09/836,947 US6385098B2 (en) | 1999-09-01 | 2001-04-17 | Method and apparatus for supplying regulated power to memory device components |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/388,126 US6219293B1 (en) | 1999-09-01 | 1999-09-01 | Method and apparatus for supplying regulated power to memory device components |
US09/836,947 US6385098B2 (en) | 1999-09-01 | 2001-04-17 | Method and apparatus for supplying regulated power to memory device components |
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US09/388,126 Continuation US6219293B1 (en) | 1999-09-01 | 1999-09-01 | Method and apparatus for supplying regulated power to memory device components |
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US20010012220A1 true US20010012220A1 (en) | 2001-08-09 |
US6385098B2 US6385098B2 (en) | 2002-05-07 |
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US09/388,126 Expired - Lifetime US6219293B1 (en) | 1999-09-01 | 1999-09-01 | Method and apparatus for supplying regulated power to memory device components |
US09/836,947 Expired - Lifetime US6385098B2 (en) | 1999-09-01 | 2001-04-17 | Method and apparatus for supplying regulated power to memory device components |
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US09/388,126 Expired - Lifetime US6219293B1 (en) | 1999-09-01 | 1999-09-01 | Method and apparatus for supplying regulated power to memory device components |
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US (2) | US6219293B1 (en) |
EP (1) | EP1218887B1 (en) |
JP (1) | JP2003508871A (en) |
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AT (1) | ATE349059T1 (en) |
AU (1) | AU7114700A (en) |
DE (1) | DE60032497T2 (en) |
WO (1) | WO2001016956A1 (en) |
Cited By (2)
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US20080291715A1 (en) * | 2006-12-28 | 2008-11-27 | Samsung Electronics Co., Ltd. | Nonvolatile memory device using variable resistive materials |
US20240021221A1 (en) * | 2022-07-13 | 2024-01-18 | Nanya Technology Corporation | Memory device, voltage generating device and voltage generating method thereof |
Families Citing this family (14)
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US6650589B2 (en) * | 2001-11-29 | 2003-11-18 | Intel Corporation | Low voltage operation of static random access memory |
US6785161B2 (en) | 2002-06-28 | 2004-08-31 | Micron Technology, Inc. | High voltage regulator for low voltage integrated circuit processes |
KR100460459B1 (en) * | 2002-07-30 | 2004-12-08 | 삼성전자주식회사 | Semiconductor memory device with improved test mode |
US6859408B2 (en) * | 2002-08-29 | 2005-02-22 | Micron Technology, Inc. | Current limiting antifuse programming path |
ITRM20030338A1 (en) * | 2003-07-11 | 2005-01-12 | Micron Technology Inc | HIGH VOLTAGE GENERATION AND REGULATION CIRCUIT |
TWM241879U (en) * | 2003-09-08 | 2004-08-21 | Well Shin Technology Co Ltd | Multi-functional adapter |
US20050149785A1 (en) * | 2003-12-19 | 2005-07-07 | Hassan Mohamed A. | Apparatus and method for testing a flash memory unit using stress voltages |
US20050138497A1 (en) * | 2003-12-19 | 2005-06-23 | Hassan Mohamed A. | Apparatus and method for testing a flash memory unit |
US6992939B2 (en) * | 2004-01-26 | 2006-01-31 | Micron Technology, Inc. | Method and apparatus for identifying short circuits in an integrated circuit device |
US7702479B2 (en) * | 2005-05-12 | 2010-04-20 | International Business Machines Corporation | On-board guard-band chamber environment emulator |
JP2007133996A (en) * | 2005-11-11 | 2007-05-31 | Toshiba Corp | Semiconductor memory and its control method |
KR102171261B1 (en) * | 2013-12-27 | 2020-10-28 | 삼성전자 주식회사 | Memory device with multiple voltage generators |
KR20180079903A (en) * | 2017-01-03 | 2018-07-11 | 삼성전자주식회사 | Device for detecting leakage current and memory device |
US11948625B2 (en) | 2021-09-09 | 2024-04-02 | Winbond Electronics Corporation | Systems on chips, memory circuits, and methods for accessing data in a memory circuit directly using a transistor-level operation signal |
Family Cites Families (4)
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US5446367A (en) * | 1993-05-25 | 1995-08-29 | Micron Semiconductor, Inc. | Reducing current supplied to an integrated circuit |
US5552739A (en) * | 1994-02-08 | 1996-09-03 | Micron Technology, Inc. | Integrated circuit power supply having piecewise linearity |
JP3155879B2 (en) * | 1994-02-25 | 2001-04-16 | 株式会社東芝 | Semiconductor integrated circuit device |
US5596534A (en) * | 1995-06-27 | 1997-01-21 | Micron Technology, Inc. | Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM |
-
1999
- 1999-09-01 US US09/388,126 patent/US6219293B1/en not_active Expired - Lifetime
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2000
- 2000-08-31 AT AT00959905T patent/ATE349059T1/en not_active IP Right Cessation
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- 2000-08-31 EP EP00959905A patent/EP1218887B1/en not_active Expired - Lifetime
- 2000-08-31 AU AU71147/00A patent/AU7114700A/en not_active Abandoned
- 2000-08-31 JP JP2001520415A patent/JP2003508871A/en active Pending
- 2000-08-31 WO PCT/US2000/024346 patent/WO2001016956A1/en active IP Right Grant
- 2000-08-31 DE DE60032497T patent/DE60032497T2/en not_active Expired - Lifetime
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2001
- 2001-04-17 US US09/836,947 patent/US6385098B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080291715A1 (en) * | 2006-12-28 | 2008-11-27 | Samsung Electronics Co., Ltd. | Nonvolatile memory device using variable resistive materials |
US20240021221A1 (en) * | 2022-07-13 | 2024-01-18 | Nanya Technology Corporation | Memory device, voltage generating device and voltage generating method thereof |
US11955196B2 (en) * | 2022-07-13 | 2024-04-09 | Nanya Technology Corporation | Memory device, voltage generating device and voltage generating method thereof |
Also Published As
Publication number | Publication date |
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EP1218887A4 (en) | 2004-10-13 |
EP1218887B1 (en) | 2006-12-20 |
AU7114700A (en) | 2001-03-26 |
EP1218887A1 (en) | 2002-07-03 |
DE60032497D1 (en) | 2007-02-01 |
JP2003508871A (en) | 2003-03-04 |
US6219293B1 (en) | 2001-04-17 |
ATE349059T1 (en) | 2007-01-15 |
KR100738828B1 (en) | 2007-07-13 |
WO2001016956A1 (en) | 2001-03-08 |
KR20020043572A (en) | 2002-06-10 |
DE60032497T2 (en) | 2007-10-04 |
US6385098B2 (en) | 2002-05-07 |
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