DE60031637D1 - Damaszene Verbindungsstruktur und ihr Herstellungsverfahren - Google Patents
Damaszene Verbindungsstruktur und ihr HerstellungsverfahrenInfo
- Publication number
- DE60031637D1 DE60031637D1 DE60031637T DE60031637T DE60031637D1 DE 60031637 D1 DE60031637 D1 DE 60031637D1 DE 60031637 T DE60031637 T DE 60031637T DE 60031637 T DE60031637 T DE 60031637T DE 60031637 D1 DE60031637 D1 DE 60031637D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing process
- connection structure
- damascene
- damascene connection
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9915669A FR2802336B1 (fr) | 1999-12-13 | 1999-12-13 | Structure d'interconnexions de type damascene et son procede de realisation |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60031637D1 true DE60031637D1 (de) | 2006-12-14 |
Family
ID=9553165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60031637T Expired - Lifetime DE60031637D1 (de) | 1999-12-13 | 2000-12-11 | Damaszene Verbindungsstruktur und ihr Herstellungsverfahren |
Country Status (4)
Country | Link |
---|---|
US (1) | US6624053B2 (de) |
EP (1) | EP1109221B1 (de) |
DE (1) | DE60031637D1 (de) |
FR (1) | FR2802336B1 (de) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020086547A1 (en) * | 2000-02-17 | 2002-07-04 | Applied Materials, Inc. | Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask |
TW535253B (en) * | 2000-09-08 | 2003-06-01 | Applied Materials Inc | Plasma treatment of silicon carbide films |
US6979903B1 (en) * | 2001-06-04 | 2005-12-27 | Advanced Micro Devices, Inc. | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
US6469385B1 (en) * | 2001-06-04 | 2002-10-22 | Advanced Micro Devices, Inc. | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
KR100668819B1 (ko) * | 2001-06-26 | 2007-01-17 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US7642202B1 (en) * | 2001-06-28 | 2010-01-05 | Novellus Systems, Inc. | Methods of forming moisture barrier for low k film integration with anti-reflective layers |
US6879046B2 (en) * | 2001-06-28 | 2005-04-12 | Agere Systems Inc. | Split barrier layer including nitrogen-containing portion and oxygen-containing portion |
US6797605B2 (en) * | 2001-07-26 | 2004-09-28 | Chartered Semiconductor Manufacturing Ltd. | Method to improve adhesion of dielectric films in damascene interconnects |
US20030064582A1 (en) * | 2001-09-28 | 2003-04-03 | Oladeji Isaiah O. | Mask layer and interconnect structure for dual damascene semiconductor manufacturing |
JP2003124189A (ja) * | 2001-10-10 | 2003-04-25 | Fujitsu Ltd | 半導体装置の製造方法 |
US7091137B2 (en) * | 2001-12-14 | 2006-08-15 | Applied Materials | Bi-layer approach for a hermetic low dielectric constant layer for barrier applications |
US6890850B2 (en) * | 2001-12-14 | 2005-05-10 | Applied Materials, Inc. | Method of depositing dielectric materials in damascene applications |
US6838393B2 (en) * | 2001-12-14 | 2005-01-04 | Applied Materials, Inc. | Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide |
KR100799118B1 (ko) * | 2001-12-19 | 2008-01-29 | 주식회사 하이닉스반도체 | 다층 구리 배선의 형성 방법 |
US20030119305A1 (en) * | 2001-12-21 | 2003-06-26 | Huang Robert Y. S. | Mask layer and dual damascene interconnect structure in a semiconductor device |
US6911389B2 (en) * | 2002-09-18 | 2005-06-28 | Texas Instruments Incorporated | Self aligned vias in dual damascene interconnect, buried mask approach |
US7749563B2 (en) * | 2002-10-07 | 2010-07-06 | Applied Materials, Inc. | Two-layer film for next generation damascene barrier application with good oxidation resistance |
GB2394879B (en) | 2002-11-04 | 2005-11-23 | Electrolux Outdoor Prod Ltd | Trimmer |
US6917108B2 (en) * | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
US6706629B1 (en) * | 2003-01-07 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Barrier-free copper interconnect |
JP3898133B2 (ja) * | 2003-01-14 | 2007-03-28 | Necエレクトロニクス株式会社 | SiCHN膜の成膜方法。 |
JP4068072B2 (ja) * | 2003-01-29 | 2008-03-26 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6913992B2 (en) | 2003-03-07 | 2005-07-05 | Applied Materials, Inc. | Method of modifying interlayer adhesion |
US7071539B2 (en) * | 2003-07-28 | 2006-07-04 | International Business Machines Corporation | Chemical planarization performance for copper/low-k interconnect structures |
US20050077629A1 (en) * | 2003-10-14 | 2005-04-14 | International Business Machines Corporation | Photoresist ash process with reduced inter-level dielectric ( ILD) damage |
US7265437B2 (en) * | 2005-03-08 | 2007-09-04 | International Business Machines Corporation | Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties |
JP2007053220A (ja) * | 2005-08-18 | 2007-03-01 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP4231055B2 (ja) * | 2006-02-06 | 2009-02-25 | 株式会社東芝 | 半導体装置及びその製造方法 |
US8618663B2 (en) | 2007-09-20 | 2013-12-31 | International Business Machines Corporation | Patternable dielectric film structure with improved lithography and method of fabricating same |
US7709370B2 (en) * | 2007-09-20 | 2010-05-04 | International Business Machines Corporation | Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures |
US8084862B2 (en) * | 2007-09-20 | 2011-12-27 | International Business Machines Corporation | Interconnect structures with patternable low-k dielectrics and method of fabricating same |
JP2010003894A (ja) * | 2008-06-20 | 2010-01-07 | Nec Electronics Corp | 半導体装置の製造方法及び半導体装置 |
US8138093B2 (en) * | 2009-08-12 | 2012-03-20 | International Business Machines Corporation | Method for forming trenches having different widths and the same depth |
JP5404365B2 (ja) * | 2009-12-16 | 2014-01-29 | キヤノン株式会社 | 電気機械変換装置及びその製造方法 |
CN104465491B (zh) * | 2013-09-23 | 2018-01-12 | 中芯国际集成电路制造(上海)有限公司 | 金属互连层的形成方法 |
FR3036849B1 (fr) | 2015-05-28 | 2018-07-13 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de realisation d'un filtre infrarouge associe a un capteur d'image |
US10380868B2 (en) * | 2016-08-25 | 2019-08-13 | Infineon Technologies Ag | Sensor devices |
US10872861B2 (en) * | 2018-02-07 | 2020-12-22 | Advanced Semiconductor Engineering, Inc. Kaohsiung, Taiwan | Semiconductor packages |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6159871A (en) * | 1998-05-29 | 2000-12-12 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6331479B1 (en) * | 1999-09-20 | 2001-12-18 | Chartered Semiconductor Manufacturing Ltd. | Method to prevent degradation of low dielectric constant material in copper damascene interconnects |
US6372661B1 (en) * | 2000-07-14 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company | Method to improve the crack resistance of CVD low-k dielectric constant material |
US6350675B1 (en) * | 2000-10-12 | 2002-02-26 | Chartered Semiconductor Manufacturing Ltd. | Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects |
-
1999
- 1999-12-13 FR FR9915669A patent/FR2802336B1/fr not_active Expired - Fee Related
-
2000
- 2000-12-06 US US09/731,090 patent/US6624053B2/en not_active Expired - Lifetime
- 2000-12-11 DE DE60031637T patent/DE60031637D1/de not_active Expired - Lifetime
- 2000-12-11 EP EP00403464A patent/EP1109221B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1109221A2 (de) | 2001-06-20 |
US6624053B2 (en) | 2003-09-23 |
FR2802336A1 (fr) | 2001-06-15 |
EP1109221A3 (de) | 2001-09-12 |
FR2802336B1 (fr) | 2002-03-01 |
US20010004550A1 (en) | 2001-06-21 |
EP1109221B1 (de) | 2006-11-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |