DE450572T1 - Verfahren zum herstellen eines versiegelten selbstjustierenden kontaktes und struktur. - Google Patents

Verfahren zum herstellen eines versiegelten selbstjustierenden kontaktes und struktur.

Info

Publication number
DE450572T1
DE450572T1 DE199191105191T DE91105191T DE450572T1 DE 450572 T1 DE450572 T1 DE 450572T1 DE 199191105191 T DE199191105191 T DE 199191105191T DE 91105191 T DE91105191 T DE 91105191T DE 450572 T1 DE450572 T1 DE 450572T1
Authority
DE
Germany
Prior art keywords
producing
adjusting contact
sealed self
sealed
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE199191105191T
Other languages
English (en)
Inventor
Douglas Colorado Springs Colorado 80919 Us Butler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RAMTRON CORP COLORADO SPRINGS COL US
UMC Japan Co Ltd
Original Assignee
RAMTRON CORP COLORADO SPRINGS COL US
NMB Semiconductor KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RAMTRON CORP COLORADO SPRINGS COL US, NMB Semiconductor KK filed Critical RAMTRON CORP COLORADO SPRINGS COL US
Publication of DE450572T1 publication Critical patent/DE450572T1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material
DE199191105191T 1990-04-05 1991-04-02 Verfahren zum herstellen eines versiegelten selbstjustierenden kontaktes und struktur. Pending DE450572T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/505,242 US5043790A (en) 1990-04-05 1990-04-05 Sealed self aligned contacts using two nitrides process

Publications (1)

Publication Number Publication Date
DE450572T1 true DE450572T1 (de) 1992-04-09

Family

ID=24009558

Family Applications (1)

Application Number Title Priority Date Filing Date
DE199191105191T Pending DE450572T1 (de) 1990-04-05 1991-04-02 Verfahren zum herstellen eines versiegelten selbstjustierenden kontaktes und struktur.

Country Status (4)

Country Link
US (2) US5043790A (de)
EP (1) EP0450572A3 (de)
JP (1) JPH0727878B2 (de)
DE (1) DE450572T1 (de)

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US5216281A (en) * 1990-04-05 1993-06-01 Ramtron Corporation Self sealed aligned contact incorporating a dopant source
JPH0490514A (ja) * 1990-08-02 1992-03-24 Semiconductor Energy Lab Co Ltd 半導体装置
DE69222390T2 (de) * 1991-10-31 1998-03-19 Sgs Thomson Microelectronics Herstellungsverfahren eines selbstjustierenden Kontakts
US5323047A (en) * 1992-01-31 1994-06-21 Sgs-Thomson Microelectronics, Inc. Structure formed by a method of patterning a submicron semiconductor layer
US5286344A (en) * 1992-06-15 1994-02-15 Micron Technology, Inc. Process for selectively etching a layer of silicon dioxide on an underlying stop layer of silicon nitride
US5880036A (en) 1992-06-15 1999-03-09 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
KR960004079B1 (en) * 1992-12-19 1996-03-26 Lg Semicon Co Ltd Contact hole forming method
JP3065829B2 (ja) * 1992-12-25 2000-07-17 新日本製鐵株式会社 半導体装置
JP3552238B2 (ja) * 1992-12-28 2004-08-11 日立金属株式会社 Ｌｓｉのオーミックコンタクト部形成方法
US5610099A (en) * 1994-06-28 1997-03-11 Ramtron International Corporation Process for fabricating transistors using composite nitride structure
DE69531282T2 (de) * 1994-12-20 2004-05-27 STMicroelectronics, Inc., Carrollton Isolierung durch aktive Transistoren mit geerdeten Torelektroden
US6380598B1 (en) 1994-12-20 2002-04-30 Stmicroelectronics, Inc. Radiation hardened semiconductor memory
JP3349001B2 (ja) * 1994-12-29 2002-11-20 ソニー株式会社 金属膜の形成方法
US5763910A (en) * 1995-01-31 1998-06-09 Fujitsu Limited Semiconductor device having a through-hole formed on diffused layer by self-alignment
JP2882352B2 (ja) * 1996-04-19 1999-04-12 日本電気株式会社 半導体装置の製造方法
DE19622415A1 (de) * 1996-06-04 1997-12-11 Siemens Ag CMOS-Halbleiterstruktur und Verfahren zur Herstellung derselben
US6091129A (en) * 1996-06-19 2000-07-18 Cypress Semiconductor Corporation Self-aligned trench isolated structure
US5830797A (en) * 1996-06-20 1998-11-03 Cypress Semiconductor Corporation Interconnect methods and apparatus
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
US6049133A (en) * 1996-06-27 2000-04-11 Advanced Micro Devices, Inc. Semiconductor fabrication employing concurrent diffusion barrier and salicide formation
US5911887A (en) * 1996-07-19 1999-06-15 Cypress Semiconductor Corporation Method of etching a bond pad
US5668065A (en) * 1996-08-01 1997-09-16 Winbond Electronics Corp. Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects
US5861676A (en) * 1996-11-27 1999-01-19 Cypress Semiconductor Corp. Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit
JP2981184B2 (ja) * 1997-02-21 1999-11-22 トーカロ株式会社 ボイラ伝熱管および管内面デポジット付着抑制効果に優れるボイラ伝熱管の製造方法
US5968851A (en) * 1997-03-19 1999-10-19 Cypress Semiconductor Corp. Controlled isotropic etch process and method of forming an opening in a dielectric layer
US5876614A (en) * 1997-04-18 1999-03-02 Storage Technology Corporation Method of wet etching aluminum oxide to minimize undercutting
US6001710A (en) * 1998-03-30 1999-12-14 Spectrian, Inc. MOSFET device having recessed gate-drain shield and method
US6235630B1 (en) * 1998-08-19 2001-05-22 Micron Technology, Inc. Silicide pattern structures and methods of fabricating the same
US6725536B1 (en) 1999-03-10 2004-04-27 Micron Technology, Inc. Methods for the fabrication of electrical connectors
WO2001011681A1 (en) * 1999-08-11 2001-02-15 Ultrarf, Inc. Mosfet device having recessed gate-drain shield and method
KR100308619B1 (ko) * 1999-08-24 2001-11-01 윤종용 반도체 장치용 자기 정렬 콘택 패드 형성 방법
US6091630A (en) * 1999-09-10 2000-07-18 Stmicroelectronics, Inc. Radiation hardened semiconductor memory
WO2001043176A1 (en) * 1999-12-08 2001-06-14 Samsung Electronics Co., Ltd. Semiconductor device having a self-aligned contact structure and methods of forming the same
US6624076B1 (en) * 2000-01-21 2003-09-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
KR100339683B1 (ko) * 2000-02-03 2002-06-05 윤종용 반도체 집적회로의 자기정렬 콘택 구조체 형성방법
US6445050B1 (en) 2000-02-08 2002-09-03 International Business Machines Corporation Symmetric device with contacts self aligned to gate
US6337278B1 (en) 2000-08-23 2002-01-08 Mosel Vitelic, Inc. Technique for forming a borderless overlapping gate and diffusion contact structure in integrated circuit device processing
US6365515B1 (en) 2000-08-28 2002-04-02 Micron Technology, Inc. Chemical vapor deposition process
US7791158B2 (en) * 2005-04-13 2010-09-07 Samsung Electronics Co., Ltd. CMOS image sensor including an interlayer insulating layer and method of manufacturing the same
CN112151450B (zh) 2019-06-26 2023-08-08 联华电子股份有限公司 半导体结构及其形成方法

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US3881078A (en) * 1974-01-15 1975-04-29 Raymond Lee Organization Inc De-acceleration switch operable by release of force on accelerator pedal
JPS58137231A (ja) * 1982-02-09 1983-08-15 Nec Corp 集積回路装置
JPS60151476A (ja) * 1984-01-14 1985-08-09 Takashi Hosokawa 電磁弁
US4570331A (en) * 1984-01-26 1986-02-18 Inmos Corporation Thick oxide field-shield CMOS process
JPS60163455A (ja) * 1984-02-03 1985-08-26 Toshiba Corp 読み出し専用記憶装置及びその製造方法
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US4811078A (en) * 1985-05-01 1989-03-07 Texas Instruments Incorporated Integrated circuit device and process with tin capacitors
US5010032A (en) * 1985-05-01 1991-04-23 Texas Instruments Incorporated Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
EP0232508B1 (de) * 1986-01-09 1992-03-11 International Business Machines Corporation Verfahren zur Herstellung eines Kontakts unter Verwendung der Erweichung zweier Glasschichten
US4826781A (en) * 1986-03-04 1989-05-02 Seiko Epson Corporation Semiconductor device and method of preparation
JPS63234548A (ja) * 1987-03-24 1988-09-29 Oki Electric Ind Co Ltd 半導体素子の製造方法
JPS63258021A (ja) * 1987-04-16 1988-10-25 Toshiba Corp 接続孔の形成方法
US4878994A (en) * 1987-07-16 1989-11-07 Texas Instruments Incorporated Method for etching titanium nitride local interconnects
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
JP2776826B2 (ja) * 1988-04-15 1998-07-16 株式会社日立製作所 半導体装置およびその製造方法
JPH01281750A (ja) * 1988-05-07 1989-11-13 Seiko Epson Corp 半導体装置
JPH01281988A (ja) * 1988-05-07 1989-11-13 Seiko Epson Corp 熱転写記録媒体
JP2904533B2 (ja) * 1989-03-09 1999-06-14 株式会社東芝 半導体装置の製造方法
US4921572A (en) * 1989-05-04 1990-05-01 Olin Corporation Etchant solutions containing hydrogen fluoride and a polyammonium fluoride salt

Also Published As

Publication number Publication date
EP0450572A2 (de) 1991-10-09
US5043790A (en) 1991-08-27
JPH076977A (ja) 1995-01-10
EP0450572A3 (en) 1994-06-01
US5385634A (en) 1995-01-31
JPH0727878B2 (ja) 1995-03-29

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