CN112151450B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN112151450B
CN112151450B CN201910559598.0A CN201910559598A CN112151450B CN 112151450 B CN112151450 B CN 112151450B CN 201910559598 A CN201910559598 A CN 201910559598A CN 112151450 B CN112151450 B CN 112151450B
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phosphorus
dielectric layer
density region
containing dielectric
forming
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CN112151450A (zh
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王祯贞
张建军
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United Microelectronics Corp
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Priority to EP20169255.5A priority patent/EP3758045A1/en
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Abstract

本发明公开一种半导体结构及其形成方法。半导体结构包括基底、栅极、及含磷的介电层。栅极在基底上。含磷的介电层在栅极上。含磷的介电层具有变化的磷掺杂质密度分布轮廓。

Description

半导体结构及其形成方法
技术领域
本发明涉及一种半导体结构及其形成方法，且特别是涉及一种晶体管及其形成方法。
背景技术
为了在半导体芯片上形成一设计的集成电路(integrated circuits)，一般是制作一光掩模，并在光掩模上形成一设计的布局(layout)图案，再通过黄光光刻(photolithography)制作工艺将光掩模上的图案转移到半导体结构表面的光致抗蚀剂层上，进而将集成电路的布局图案转移到半导体结构上。所以光刻制作工艺可说是半导体制作工艺中非常重要的关键步骤。
由于在光掩模上所能制作出的图案的临界尺寸(critical dimension,CD)会受限于曝光机台(optical exposure tool)的分辨率极限(resolution limit)，因此当集成度(integration)逐渐提高，电路图案设计越来越小，在对这些高密度排列的光掩模进行曝光制作工艺以进行图案转移时，很容易产生光学接近效应(optical proximity effect,OPE)，造成图案转移的偏差(deviation)或是图案变形而影响产品电性特征。
发明内容
本发明提供一种半导体结构及其形成方法，以解决上述问题。
本发明提出一种半导体结构的形成方法，其包括以下步骤。形成栅极，方法包括形成栅介电层于基底上；形成栅电极于栅介电层上；及形成氮化物间隙壁于栅电极的侧壁上。形成含磷的介电层于栅极上。含磷的介电层具有变化的磷掺杂质密度分布轮廓。
本发明另提出一种半导体结构，其包括基底、栅极、及含磷的介电层。栅极在基底上。含磷的介电层在栅极上。含磷的介电层具有变化的磷掺杂质密度分布轮廓。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附的附图详细说明如下：
附图说明
图1为一实施例的半导体结构的形成方法的示意图；
图1A为一实施例的半导体结构的形成方法的示意图；
图1B为一实施例的半导体结构的形成方法的示意图；
图1C为一实施例的半导体结构的形成方法的示意图；
图2为一实施例的半导体结构的形成方法的示意图；
图3为一实施例的半导体结构的形成方法的示意图。
具体实施方式
以下以一些实施例做说明。需注意的是，本发明并非显示出所有可能的实施例，未于本发明提出的其他实施态样也可能可以应用。再者，附图上的尺寸比例并非按照实际产品等比例绘制。因此，说明书和图示内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。另外，实施例中之叙述，例如细部结构、制作工艺步骤和材料应用等等，仅为举例说明之用，并非对本发明欲保护的范围做限缩。实施例的步骤和结构各细节可在不脱离本发明的精神和范围内根据实际应用制作工艺的需要而加以变化与修饰。以下是以相同/类似的符号表示相同/类似的元件做说明。
请参照图1，其绘示根据一实施例的半导体结构的形成方法。提供基底102。基底102可包括含硅基底，或其它合适的半导体基底。可形成隔离元件104于基底102中，以在基底102中定义出不同的主动(有源)区域。例如图1所示的两个主动区域其中之一为P型装置区域，其中之另一为N型装置区域。隔离元件104可包括浅沟槽隔离结构，但不限于此，也可使用其它合适的隔离结构。形成栅介电层106于基底102上。栅介电层106可包括氧化物(例如氧化硅)、氮化物(例如氮化硅)、或其它合适的介电材料。形成栅电极108于栅介电层106上。栅电极108可包括多晶硅、非晶硅、或其它具有导电性质的合适材料。栅介电层106与栅电极108可利用适合的沉积制作工艺形成毯覆性层膜(未显示)，然后，利用黄光光刻制作工艺与蚀刻制作工艺图案化层膜所形成。沉积制作工艺可包括化学气相沉积方法、物理气相沉积方法等，但不限于此，也可使用其它合适的沉积方式。可形成氮化物间隙壁110于栅电极108与栅介电层106的侧壁上。氮化物间隙壁110的形成方式可包括利用适合的沉积制作工艺形成毯覆性层膜(未显示)，然后，对层膜进行各向异性蚀刻制作工艺，蚀刻制作工艺留下位于栅电极108与栅介电层106的侧壁上的部分层膜是形成氮化物间隙壁110。沉积制作工艺可包括化学气相沉积方法、物理气相沉积方法等，但不限于此，也可使用其它合适的沉积方式。氮化物间隙壁110可具有由上至下逐渐变大的宽度。氮化物间隙壁110包括氮化硅(SiN)。蚀刻制作工艺可包括干式蚀刻、湿式蚀刻、或其它合适的蚀刻方式。栅极112可包括栅介电层106、栅电极108与氮化物间隙壁110。形成源/漏极114在基底102中。源/漏极114可利用掺杂基底102的方式形成。晶体管可包括栅极112与源/漏极114。栅电极108与源/漏极114可包括利用金属硅化方法形成在顶部的金属硅化物。
请参照图1，形成含磷的介电层216于栅极112、源/漏极114与隔离元件104上。实施例中，含磷的介电层216的形成方法包括使用高密度等离子体化学气相沉积(high densityplasma chemical vapor deposition；HDPCVD)、次常压化学气相沉积(sub-atmospherechemical vapor deposition；SACVD)、或其它合适的方法。含磷的介电层216可包括磷硅玻璃(phosphosilcate glass,PSG)、硼磷硅玻璃(borophophosphosilcate glass,BPSG)、或其它合适的含磷介电材料。含磷的介电层216的磷含量可约为6wt％～12wt％，或在更高的含量，一实施例中，磷含量例如为约9wt％。
实施例中，含磷的介电层216具有变化的磷掺杂质密度分布轮廓。详细来说，含磷的介电层216包括膜部分218与对应于栅极112的类火焰轮廓部分220。类火焰轮廓部分220包括磷掺杂质密度区域222与磷掺杂质密度区域224。磷掺杂质密度区域222(第一磷掺杂质密度区域)在栅电极108的上表面上。磷掺杂质密度区域222可具有从底部分至顶部分逐渐变小的宽度。磷掺杂质密度区域222可具有相对的两平直的侧表面222S。一实施例中，磷掺杂质密度区域222可具有类三角形状，侧表面222S之间可定义出顶点222P。磷掺杂质密度区域224(第二磷掺杂质密度区域)可位于磷掺杂质密度区域222的侧表面222S上。磷掺杂质密度区域224也可位于氮化物间隙壁110的侧表面上。磷掺杂质密度区域224可具有彼此相对的两凸状的侧表面224S，侧表面224S之间可定义出顶点224P。类火焰轮廓部分220可具有不对称的形状，例如，定义在磷掺杂质密度区域222的顶点222P与磷掺杂质密度区域224的顶点224P之间的直线226可偏离垂直方向(例如，正交于基底102之上表面的方向)。含磷的介电层216的膜部分218位于类火焰轮廓部分220、源/漏极114与隔离元件104上。
在一实施例中，磷掺杂质密度区域222的磷掺杂质密度是高于磷掺杂质密度区域224的磷掺杂质密度。膜部分218的磷掺杂质密度是高于磷掺杂质密度区域224的磷掺杂质密度。磷掺杂质密度区域222与膜部分218可具有实质上相同的磷掺杂质密度。举例来说，磷掺杂质密度区域222与膜部分218的磷含量可为9％，磷掺杂质密度区域224的磷含量可低于磷掺杂质密度区域222与膜部分218的磷含量0.3～1wt％，也就是说磷掺杂质密度区域224的磷含量可为8～8.7wt％。
在另一实施例中，磷掺杂质密度区域222的磷掺杂质密度可实质上等于磷掺杂质密度区域224的磷掺杂质密度。膜部分218的磷掺杂质密度可高于磷掺杂质密度区域222的磷掺杂质密度，并高于磷掺杂质密度区域224的磷掺杂质密度。举例来说，膜部分218的磷含量可为9％，磷掺杂质密度区域222与磷掺杂质密度区域224的磷含量可低于膜部分218的磷含量0.3～1wt％，也就是说，磷掺杂质密度区域222的磷含量可为8～8.7wt％，磷掺杂质密度区域224的磷含量可为8～8.7wt％。
在一实施例中，图1所示的含磷的介电层216可为利用高密度等离子体化学气相沉积制作工艺所形成的初始(initial)膜层。一实施例中，高密度等离子体化学气相沉积的制作工艺参数可举例如下。低频功率(LF power)可为3000W～4000W。高频功率(HF power)为1500W～2500W。氦气(He)流量为100sccm～200sccm。氧气(O2)流量为400sccm～800sccm。磷化氢(PH3)气体流量为100sccm～180sccm。硅甲烷(SiH4)气体流量为20sccm～100sccm。在一实施例中，反应腔室中的磷化氢：硅甲烷的气体含量比为1：1。反应腔室压力为0.2Torr～1Torr。温度(例如基板温度或放置基板之平台的温度)为200℃～650℃。沉积厚度设定为沉积速率设定为/> 溅射速率为沉积膜的磷含量为6wt％～12wt％。在一实施例中，膜部分218、磷掺杂质密度区域222与磷掺杂质密度区域224都为磷硅玻璃(PSG)或硼硅玻璃(BSG)或硼磷硅玻璃(BPSG)，但本发明不限于此。
在另一实施例中，如图1A所示的半导体结构，其中膜部分218具有平坦的上表面218T。
在又另一实施例中，如图1B所示的半导体结构，其中含磷的介电层216的磷掺杂质密度区域224的上表面224T可为一平坦的上表面。此实施例中，含磷的介电层216包括膜部分218与对应于栅极112的类花苞轮廓部分221。类花苞轮廓部分221包括磷掺杂质密度区域222与磷掺杂质密度区域224。类花苞轮廓部分221的磷掺杂质密度区域224可具有彼此相对的两凸状的侧表面224S，以及在侧表面224S之间的上表面224T。磷掺杂质密度区域224的上表面224T可实质上齐平膜部分218的上表面218T。
在又再另一实施例中，如图1C所示的半导体结构，其中含磷的介电层216的磷掺杂质密度区域222的上表面222T可为一平坦的上表面。此实施例中，含磷的介电层216包括膜部分218与对应于栅极112的类花苞轮廓部分221。类花苞轮廓部分221包括磷掺杂质密度区域222与磷掺杂质密度区域224。类花苞轮廓部分221的磷掺杂质密度区域222可具有彼此相对的两平直的侧表面222S，以及在侧表面222S之间的上表面222T。类花苞轮廓部分221的磷掺杂质密度区域224可具有彼此相对的两凸状的侧表面224S，以及上表面224T。磷掺杂质密度区域224的上表面224T在侧表面224S与磷掺杂质密度区域222的侧表面222S之间。磷掺杂质密度区域222的上表面222T可实质上齐平磷掺杂质密度区域224的上表面224T，并齐平膜部分218的上表面218T。
图1A、图1B与图1C所示的半导体结构的含磷的介电层216可能通过伴随高密度等离子体化学气相沉积制作工艺的蚀刻制作工艺形成，或者可利用化学机械研磨方法对含磷的介电层216的上表面进行平坦化制作工艺所形成。
实施例中，半导体结构的形成方法可包括对含磷的介电层216进行蚀刻步骤。在一实施例中，用以移除含磷的介电层216(例如PSG或BPSG)的蚀刻步骤对于氮化物材料(例如SiN)具有高的蚀刻选择性。换句话说，用以移除含磷的介电层216的蚀刻步骤对于含磷的介电层216的蚀刻速率可显著大于对氮化物材料的蚀刻速率。或甚至，当利用蚀刻步骤移除含磷的介电层216时，露出于蚀刻环境的氮化物材料实质上不会被移除。含磷的介电层216亦可达到充分填充栅极112之间的间隙的需求。含磷的介电层216可用作层间介电层。
请参照图2，其绘示根据一实施例的半导体结构的形成方法。含磷的介电层216可利用参照图1、图1A、图1B、或图1C所述的方式形成。可形成盖层328在含磷的介电层216上。盖层328可包括四乙氧基硅烷(TEOS)，但不限于此，也可使用其它合适的材料。盖层328可使用化学气相沉积法、物理气相沉积法、或其它合适的方法形成。盖层328可用作层间介电层。
可进行蚀刻步骤移除部分的盖层328与含磷的介电层216，以形成露出源/漏极114的接触开口(opening)330。蚀刻步骤可包括干式蚀刻、湿式蚀刻、或其它合适的方式的蚀刻制作工艺。此外，形成接触元件332(例如源/漏极114的接触窗(contact via))填充在接触开口330中。接触元件332可包括金属例如铝、钨等，或其它合适的导电材料。接触元件332的形成方法可包括物理气相沉积、化学气相沉积、或其它合适的方法。
在一实施例中，举例来说，接触开口330的形成方法可包括利用黄光光刻制作工艺，将光掩模的图案转移至形成在盖层328上的光致抗蚀剂层(未显示)，并利用蚀刻制作工艺将光致抗蚀剂层的图案向下转移至盖层328与含磷的介电层216从而形成接触开口330，然后，可移除光致抗蚀剂层。
在一实施例中，用以形成接触开口330的黄光光刻制作工艺可能图案转移的位置偏差，造成形成的接触开口330的位置偏移靠近栅极112，而甚至使得氮化物间隙壁110露出接触开口330。也就是说，氮化物间隙壁110可能会暴露于用以移除含磷的介电层216的蚀刻制作工艺。实施例中，用以形成接触开口330的蚀刻步骤对于参照图1所述方式形成的含磷的介电层216具有高的蚀刻选择性，因此，即使氮化物间隙壁110(例如氮化硅)暴露于此蚀刻环境，氮化物间隙壁110仍能不被蚀穿，甚至可用作蚀刻掩模。也就是说，接触开口330/接触元件332可利用自对准方式形成。从而，能避免接触元件332与栅极112(例如栅电极108)之间的短接问题。提升制作工艺裕度(process window)。
请参照图3，其绘示根据一实施例的半导体结构的形成方法。间隙壁410可形成于栅介电层106与栅电极108的侧壁上。栅极412可包括栅介电层106、栅电极108与间隙壁410。晶体管可包括栅极412与形成在基底102中的源/漏极114。氮化物层间介电层534可毯覆形成在栅极412与形成在基底102中的隔离元件104上。氮化物层间介电层534可使用化学气相沉积法、物理气相沉积法、或其它合适的方法形成。在一实施例中，氮化物层间介电层534可为共形于栅极412与隔离元件104的层膜。含磷的介电层216可形成在氮化物层间介电层534上。含磷的介电层216也可达到充分氮化物层间介电层534的突出部分(即对应在栅极412上方的部分)之间的间隙的需求。盖层328可形成在含磷的介电层216上。
可进行蚀刻步骤移除部分的盖层328、含磷的介电层216与氮化物层间介电层534，以形成露出源/漏极114的接触开口530。蚀刻步骤可包括干式蚀刻、湿式蚀刻、或其它合适的方式的蚀刻制作工艺。此外，形成接触元件332(例如源/漏极的接触窗)填充在接触开口530中。
在一实施例中，举例来说，举例来说，图3所示的接触开口530的形成方法可包括利用黄光光刻制作工艺，将光掩模的图案转移至形成在盖层328上的光致抗蚀剂层(未显示)，并利用蚀刻制作工艺将光致抗蚀剂层的图案依序向下转移至盖层328、含磷的介电层216与氮化物层间介电层534从而形成接触开口530，然后，可移除光致抗蚀剂层。
在一实施例中，用以形成接触开口530的蚀刻制作工艺可使用分开执行的不同蚀刻步骤。详细而言，举例来说，可先进行第一蚀刻步骤移除盖层328与含磷的介电层216，然后，进行第二蚀刻步骤移除氮化物层间介电层534。第一蚀刻步骤可不同于第二蚀刻步骤。第一蚀刻步骤可对含磷的介电层216具有高的蚀刻选择性，因此，第一蚀刻步骤可停止在氮化物层间介电层534(例如氮化硅)。然后，第二蚀刻步骤可针对移除氮化物层间介电层534采用不同于第一蚀刻步骤的其它适当的蚀刻剂或蚀刻参数、方法。第二蚀刻步骤也可使用已经被图案化的含磷的介电层216/盖层328作为蚀刻掩模。
在一实施例中，用以形成接触开口530的黄光光刻制作工艺可能图案转移的位置偏差，造成形成的接触开口530的位置偏移靠近栅极412，而甚至使得间隙壁410露出接触开口530。也就是说，间隙壁410可能会暴露于用以移除氮化物层间介电层534的蚀刻制作工艺(第二蚀刻步骤)。在一实施例中，第二蚀刻步骤对于氮化物层间介电层534具有高的蚀刻选择性，而实质上不会蚀刻间隙壁410(材料不同于氮化物层间介电层534，例如间隙壁410包括氧化物例如氧化硅或其它合适的材料)，因此，即使间隙壁410暴露于此蚀刻环境，间隙壁410仍能不被蚀穿，甚至可用作第二蚀刻步骤的蚀刻掩模。也就是说，接触开口530/接触元件332可利用自对准方式形成。从而，能避免接触元件332与栅极412(例如栅电极108)之间的短接问题。提升制作工艺裕度。
综上所述，根据实施例的半导体结构的形成方法，接触开口/接触元件可利用自对准方式形成。从而，能避免接触元件与栅极之间的短接问题。提升制作工艺裕度。
综上所述，虽然结合以上实施例公开了本发明，然而其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (16)

1.一种半导体结构的形成方法，包括：
形成栅极，方法包括：
形成栅介电层于基底上；
形成栅电极于该栅介电层上；及
形成氮化物间隙壁于该栅电极的侧壁上；及
形成含磷的介电层于该栅极上，其中该含磷的介电层具有一变化的磷掺杂质密度分布轮廓,
其中该含磷的介电层包括：
第一磷掺杂质密度区域，在该栅极上，并具有一顶点；
第二磷掺杂质密度区域，在该第一磷掺杂质密度区域上，并具有一另一顶点，其中定义在该第一磷掺杂质密度区域的该顶点与该第二磷掺杂质密度区域的该另一顶点之间的直线是偏离一垂直方向, 该第一磷掺杂质密度区域的磷掺杂质密度是高于与该第二磷掺杂质密度区域的磷掺杂质密度。
2.如权利要求1所述的半导体结构的形成方法，其中该含磷的介电层具有类火焰轮廓部分或类花苞轮廓部分。
3.如权利要求1所述的半导体结构的形成方法，其中该含磷的介电层具有数个类火焰轮廓部分或类花苞轮廓部分，分别对应多个栅极。
4.如权利要求1所述的半导体结构的形成方法，其中该含磷的介电层包括第一磷掺杂质密度区域，该第一磷掺杂质密度区域在该栅极的上表面上，并具有从该第一磷掺杂质密度区域的底部分至顶部分逐渐变小的宽度。
5.如权利要求1所述的半导体结构的形成方法，其中该含磷的介电层包括第一磷掺杂质密度区域，该第一磷掺杂质密度区域在该栅极的上表面上，并具有类三角形状。
6.如权利要求1所述的半导体结构的形成方法，还包括进行蚀刻步骤，该蚀刻步骤对该含磷的介电层具有蚀刻选择性。
7.如权利要求6所述的半导体结构的形成方法，包括通过该蚀刻步骤在该含磷的介电层中形成一接触开口。
8.如权利要求7所述的半导体结构的形成方法，还包括形成接触元件在该接触开口中。
9.如权利要求7所述的半导体结构的形成方法，还包括形成源/漏极在该基底中，其中该接触开口露出该源/漏极与该氮化物间隙壁。
10.如权利要求1所述的半导体结构的形成方法，其中该含磷的介电层包括磷硅玻璃或硼磷硅玻璃，且该氮化物间隙壁包括氮化硅。
11.如权利要求1所述的半导体结构的形成方法，其中该氮化物间隙壁具有由上至下逐渐变大的宽度。
12.如权利要求1所述的半导体结构的形成方法，其中该含磷的介电层的形成方法包括高密度等离子体化学气相沉积方法。
13.如权利要求12所述的半导体结构的形成方法，其中该高密度等离子体化学气相沉积的制作工艺参数包括：
沉积速率为5500Å/分～6500Å/分；及
溅射速率为700Å/分～1000Å/分。
14.一种半导体结构，其特征在于，包括：
基底；
栅极，在该基底上；及
含磷的介电层，在该栅极上，其中该含磷的介电层具有变化的磷掺杂质密度分布轮廓，
其中该含磷的介电层包括：
第一磷掺杂质密度区域，在该栅极上，并具有一顶点；
第二磷掺杂质密度区域，在该第一磷掺杂质密度区域上，并具有一另一顶点，其中定义在该第一磷掺杂质密度区域的该顶点与该第二磷掺杂质密度区域的该另一顶点之间的直线是偏离一垂直方向, 该第一磷掺杂质密度区域的磷掺杂质密度是高于与该第二磷掺杂质密度区域的磷掺杂质密度。
15.如权利要求14所述的半导体结构，其中该含磷的介电层具有类火焰轮廓部分或类花苞轮廓部分。
16.如权利要求14所述的半导体结构，其是以如权利要求1至13其中之一所述的半导体结构的形成方法形成。
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