DE4335457A1 - Verfahren zur Bildung eines Gate-Isolationsfilms einer Halbleitervorrichtung - Google Patents

Verfahren zur Bildung eines Gate-Isolationsfilms einer Halbleitervorrichtung

Info

Publication number
DE4335457A1
DE4335457A1 DE4335457A DE4335457A DE4335457A1 DE 4335457 A1 DE4335457 A1 DE 4335457A1 DE 4335457 A DE4335457 A DE 4335457A DE 4335457 A DE4335457 A DE 4335457A DE 4335457 A1 DE4335457 A1 DE 4335457A1
Authority
DE
Germany
Prior art keywords
film
oxide film
nitriding
gate insulation
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE4335457A
Other languages
German (de)
English (en)
Inventor
Hyun Sang Hwang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of DE4335457A1 publication Critical patent/DE4335457A1/de
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE4335457A 1992-10-20 1993-10-18 Verfahren zur Bildung eines Gate-Isolationsfilms einer Halbleitervorrichtung Ceased DE4335457A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920019239A KR960002066B1 (ko) 1992-10-20 1992-10-20 옥시 나이트라이드 제조방법

Publications (1)

Publication Number Publication Date
DE4335457A1 true DE4335457A1 (de) 1994-04-21

Family

ID=19341412

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4335457A Ceased DE4335457A1 (de) 1992-10-20 1993-10-18 Verfahren zur Bildung eines Gate-Isolationsfilms einer Halbleitervorrichtung

Country Status (4)

Country Link
JP (1) JPH06209009A (enrdf_load_stackoverflow)
KR (1) KR960002066B1 (enrdf_load_stackoverflow)
DE (1) DE4335457A1 (enrdf_load_stackoverflow)
TW (1) TW228613B (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5103478B2 (ja) 2007-09-10 2012-12-19 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
JP4902716B2 (ja) 2008-11-20 2012-03-21 株式会社日立国際電気 不揮発性半導体記憶装置およびその製造方法

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
et.al.: Characteristics of Thermal Si- licon Nitride Films Grown in Argon-Diluted Ammo- nia. In: Analytical Chemistry, 1987, H.7., S.1799-1802 *
et.al.: Improved ultrathin oxynitri-de formed by thermal nitridation and low pressure chemical vapor deposition process. In: Appl.Phys. Lett., 61, 15, 12. Oct. 1992, S.1790-1792 *
et.al.: Nitridation and Post-Ni-tridation Anneals of SiO¶2¶ for Ultrathin Dielec- trics. In: IEEE Transactions on Electron Devices, Vol.37, No.8, Aug.1990, S.1836-1841 *
MAITI, Bikas *
MOSLEHI, Mehrdad M. *
SARASWAT, Krishna C.: ThermalNitridation of Si and SiO¶2¶ for VLSI. In: IEEE Journal of Solid-State Circuits, Vol.SC-20,No.1, Feb.1985, S.26-43 *
SUN, S.W. *
WRIGHT, Peter J. *

Also Published As

Publication number Publication date
KR940010209A (ko) 1994-05-24
JPH06209009A (ja) 1994-07-26
TW228613B (enrdf_load_stackoverflow) 1994-08-21
KR960002066B1 (ko) 1996-02-10

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Legal Events

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OR8 Request for search as to paragraph 43 lit. 1 sentence 1 patent law
8105 Search report available
8110 Request for examination paragraph 44
8131 Rejection