DE4109046A1 - Digitaler pll-schaltkreis - Google Patents

Digitaler pll-schaltkreis

Info

Publication number
DE4109046A1
DE4109046A1 DE19914109046 DE4109046A DE4109046A1 DE 4109046 A1 DE4109046 A1 DE 4109046A1 DE 19914109046 DE19914109046 DE 19914109046 DE 4109046 A DE4109046 A DE 4109046A DE 4109046 A1 DE4109046 A1 DE 4109046A1
Authority
DE
Germany
Prior art keywords
pulse
output
pll circuit
phase detector
brm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19914109046
Other languages
German (de)
English (en)
Other versions
DE4109046C2 (enrdf_load_stackoverflow
Inventor
Georg Dipl Ing Steinbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alstom Power Conversion GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Priority to DE19914109046 priority Critical patent/DE4109046A1/de
Publication of DE4109046A1 publication Critical patent/DE4109046A1/de
Application granted granted Critical
Publication of DE4109046C2 publication Critical patent/DE4109046C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE19914109046 1990-04-03 1991-03-15 Digitaler pll-schaltkreis Granted DE4109046A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19914109046 DE4109046A1 (de) 1990-04-03 1991-03-15 Digitaler pll-schaltkreis

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4011121 1990-04-03
DE19914109046 DE4109046A1 (de) 1990-04-03 1991-03-15 Digitaler pll-schaltkreis

Publications (2)

Publication Number Publication Date
DE4109046A1 true DE4109046A1 (de) 1991-10-10
DE4109046C2 DE4109046C2 (enrdf_load_stackoverflow) 1993-04-15

Family

ID=25891938

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19914109046 Granted DE4109046A1 (de) 1990-04-03 1991-03-15 Digitaler pll-schaltkreis

Country Status (1)

Country Link
DE (1) DE4109046A1 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19653129C2 (de) * 1996-12-19 1999-01-28 Siemens Ag Verfahren zum Erzeugen eines Ansteuersignals für einen spannungsgesteuerten Oszillator in einem Phasenregelkreis

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3886459A (en) * 1973-08-07 1975-05-27 Usm Corp Digital pulse rate ramping circuits
DE2347839B2 (de) * 1973-09-22 1977-05-05 Robert Bosch Gmbh, 7000 Stuttgart Phasenregelkreis
US4166249A (en) * 1978-02-15 1979-08-28 Honeywell Inc. Digital frequency-lock circuit
US4418318A (en) * 1981-03-10 1983-11-29 Frederick Electronics Corporation Digital phase-locked loop circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3886459A (en) * 1973-08-07 1975-05-27 Usm Corp Digital pulse rate ramping circuits
DE2347839B2 (de) * 1973-09-22 1977-05-05 Robert Bosch Gmbh, 7000 Stuttgart Phasenregelkreis
US4166249A (en) * 1978-02-15 1979-08-28 Honeywell Inc. Digital frequency-lock circuit
US4418318A (en) * 1981-03-10 1983-11-29 Frederick Electronics Corporation Digital phase-locked loop circuit

Also Published As

Publication number Publication date
DE4109046C2 (enrdf_load_stackoverflow) 1993-04-15

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: CEGELEC AEG ANLAGEN UND ANTRIEBSSYSTEME GMBH, 1227

8327 Change in the person/name/address of the patent owner

Owner name: ALSTOM POWER CONVERSION GMBH, 12277 BERLIN, DE

8339 Ceased/non-payment of the annual fee