DE4040356C2 - - Google Patents
Info
- Publication number
- DE4040356C2 DE4040356C2 DE4040356A DE4040356A DE4040356C2 DE 4040356 C2 DE4040356 C2 DE 4040356C2 DE 4040356 A DE4040356 A DE 4040356A DE 4040356 A DE4040356 A DE 4040356A DE 4040356 C2 DE4040356 C2 DE 4040356C2
- Authority
- DE
- Germany
- Prior art keywords
- silicon
- gaas
- substrate
- sapphire
- sos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2921—Materials being crystalline insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3204—Materials thereof being Group IVA semiconducting materials
- H10P14/3211—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3258—Crystal orientation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3421—Arsenides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011561A JPH088214B2 (ja) | 1990-01-19 | 1990-01-19 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE4040356A1 DE4040356A1 (de) | 1991-07-25 |
| DE4040356C2 true DE4040356C2 (https=) | 1993-06-09 |
Family
ID=11781350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE4040356A Granted DE4040356A1 (de) | 1990-01-19 | 1990-12-17 | Halbleiterbauteil |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5081519A (https=) |
| JP (1) | JPH088214B2 (https=) |
| DE (1) | DE4040356A1 (https=) |
Families Citing this family (52)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6039803A (en) * | 1996-06-28 | 2000-03-21 | Massachusetts Institute Of Technology | Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon |
| US5955776A (en) * | 1996-12-04 | 1999-09-21 | Ball Semiconductor, Inc. | Spherical shaped semiconductor integrated circuit |
| US6423990B1 (en) | 1997-09-29 | 2002-07-23 | National Scientific Corporation | Vertical heterojunction bipolar transistor |
| US5912481A (en) | 1997-09-29 | 1999-06-15 | National Scientific Corp. | Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction |
| US6849472B2 (en) * | 1997-09-30 | 2005-02-01 | Lumileds Lighting U.S., Llc | Nitride semiconductor device with reduced polarization fields |
| JP3180743B2 (ja) * | 1997-11-17 | 2001-06-25 | 日本電気株式会社 | 窒化化合物半導体発光素子およびその製法 |
| JP2001127326A (ja) * | 1999-08-13 | 2001-05-11 | Oki Electric Ind Co Ltd | 半導体基板及びその製造方法、並びに、この半導体基板を用いた太陽電池及びその製造方法 |
| US6693033B2 (en) | 2000-02-10 | 2004-02-17 | Motorola, Inc. | Method of removing an amorphous oxide from a monocrystalline surface |
| US6392257B1 (en) * | 2000-02-10 | 2002-05-21 | Motorola Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
| KR20030011083A (ko) * | 2000-05-31 | 2003-02-06 | 모토로라 인코포레이티드 | 반도체 디바이스 및 이를 제조하기 위한 방법 |
| US6501973B1 (en) | 2000-06-30 | 2002-12-31 | Motorola, Inc. | Apparatus and method for measuring selected physical condition of an animate subject |
| US6590236B1 (en) | 2000-07-24 | 2003-07-08 | Motorola, Inc. | Semiconductor structure for use with high-frequency signals |
| AU2001277001A1 (en) * | 2000-07-24 | 2002-02-05 | Motorola, Inc. | Heterojunction tunneling diodes and process for fabricating same |
| US6555946B1 (en) | 2000-07-24 | 2003-04-29 | Motorola, Inc. | Acoustic wave device and process for forming the same |
| US6493497B1 (en) | 2000-09-26 | 2002-12-10 | Motorola, Inc. | Electro-optic structure and process for fabricating same |
| US6638838B1 (en) | 2000-10-02 | 2003-10-28 | Motorola, Inc. | Semiconductor structure including a partially annealed layer and method of forming the same |
| US6498643B1 (en) | 2000-11-13 | 2002-12-24 | Ball Semiconductor, Inc. | Spherical surface inspection system |
| US6501121B1 (en) | 2000-11-15 | 2002-12-31 | Motorola, Inc. | Semiconductor structure |
| US6559471B2 (en) | 2000-12-08 | 2003-05-06 | Motorola, Inc. | Quantum well infrared photodetector and method for fabricating same |
| US20020096683A1 (en) * | 2001-01-19 | 2002-07-25 | Motorola, Inc. | Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate |
| US6673646B2 (en) | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
| WO2002082551A1 (en) | 2001-04-02 | 2002-10-17 | Motorola, Inc. | A semiconductor structure exhibiting reduced leakage current |
| US6709989B2 (en) | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
| US7198671B2 (en) * | 2001-07-11 | 2007-04-03 | Matsushita Electric Industrial Co., Ltd. | Layered substrates for epitaxial processing, and device |
| US6992321B2 (en) | 2001-07-13 | 2006-01-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials |
| US20030010992A1 (en) * | 2001-07-16 | 2003-01-16 | Motorola, Inc. | Semiconductor structure and method for implementing cross-point switch functionality |
| US6531740B2 (en) | 2001-07-17 | 2003-03-11 | Motorola, Inc. | Integrated impedance matching and stability network |
| US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
| US6498358B1 (en) | 2001-07-20 | 2002-12-24 | Motorola, Inc. | Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating |
| US6693298B2 (en) | 2001-07-20 | 2004-02-17 | Motorola, Inc. | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same |
| US7019332B2 (en) | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
| US6855992B2 (en) * | 2001-07-24 | 2005-02-15 | Motorola Inc. | Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same |
| US6667196B2 (en) | 2001-07-25 | 2003-12-23 | Motorola, Inc. | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method |
| US6589856B2 (en) | 2001-08-06 | 2003-07-08 | Motorola, Inc. | Method and apparatus for controlling anti-phase domains in semiconductor structures and devices |
| US6639249B2 (en) | 2001-08-06 | 2003-10-28 | Motorola, Inc. | Structure and method for fabrication for a solid-state lighting device |
| US20030034491A1 (en) | 2001-08-14 | 2003-02-20 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices for detecting an object |
| US6673667B2 (en) | 2001-08-15 | 2004-01-06 | Motorola, Inc. | Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials |
| US20030036217A1 (en) * | 2001-08-16 | 2003-02-20 | Motorola, Inc. | Microcavity semiconductor laser coupled to a waveguide |
| US20030071327A1 (en) * | 2001-10-17 | 2003-04-17 | Motorola, Inc. | Method and apparatus utilizing monocrystalline insulator |
| US6916717B2 (en) | 2002-05-03 | 2005-07-12 | Motorola, Inc. | Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate |
| US20040012037A1 (en) * | 2002-07-18 | 2004-01-22 | Motorola, Inc. | Hetero-integration of semiconductor materials on silicon |
| US20040069991A1 (en) * | 2002-10-10 | 2004-04-15 | Motorola, Inc. | Perovskite cuprate electronic device structure and process |
| US20040070312A1 (en) * | 2002-10-10 | 2004-04-15 | Motorola, Inc. | Integrated circuit and process for fabricating the same |
| US7169619B2 (en) | 2002-11-19 | 2007-01-30 | Freescale Semiconductor, Inc. | Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process |
| US6885065B2 (en) | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
| US7020374B2 (en) * | 2003-02-03 | 2006-03-28 | Freescale Semiconductor, Inc. | Optical waveguide structure and method for fabricating the same |
| US6965128B2 (en) * | 2003-02-03 | 2005-11-15 | Freescale Semiconductor, Inc. | Structure and method for fabricating semiconductor microresonator devices |
| US20040164315A1 (en) * | 2003-02-25 | 2004-08-26 | Motorola, Inc. | Structure and device including a tunneling piezoelectric switch and method of forming same |
| JP4794425B2 (ja) * | 2006-12-19 | 2011-10-19 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
| US8541769B2 (en) | 2010-11-09 | 2013-09-24 | International Business Machines Corporation | Formation of a graphene layer on a large substrate |
| US9275861B2 (en) | 2013-06-26 | 2016-03-01 | Globalfoundries Inc. | Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures |
| JP6455468B2 (ja) | 2016-03-09 | 2019-01-23 | Jfeスチール株式会社 | 方向性電磁鋼板の製造方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2704223B2 (ja) * | 1987-12-28 | 1998-01-26 | 京セラ株式会社 | 半導体素子 |
| JP2704224B2 (ja) * | 1987-12-28 | 1998-01-26 | 京セラ株式会社 | 半導体素子及びその製法 |
-
1990
- 1990-01-19 JP JP2011561A patent/JPH088214B2/ja not_active Expired - Lifetime
- 1990-09-13 US US07/581,794 patent/US5081519A/en not_active Expired - Fee Related
- 1990-12-17 DE DE4040356A patent/DE4040356A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| US5081519A (en) | 1992-01-14 |
| JPH088214B2 (ja) | 1996-01-29 |
| JPH03215934A (ja) | 1991-09-20 |
| DE4040356A1 (de) | 1991-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE4040356C2 (https=) | ||
| DE68909270T2 (de) | Halbleiter-Dünnschicht und Herstellungsverfahren. | |
| DE69120116T2 (de) | Heterostruktur-Halbleiteranordnung | |
| DE10392313B4 (de) | Auf Galliumnitrid basierende Vorrichtungen und Herstellungsverfahren | |
| DE60030279T2 (de) | Halbleiterbasis, ihre herstellungsmethode und halbleiterkristallherstellungsmethode | |
| DE60033800T2 (de) | Gan-halbleiterverbundkristall-wachsmethode und halbleitersubstrat | |
| DE2416550C2 (de) | Verfahren zum Herstellen eines Halbleiterbauelements mit versetzungsfreiem Übergitterstrukturkristall | |
| DE60200261T2 (de) | Kristall einer Verbindung und Verfahren zur deren Herstellung | |
| DE4118593C2 (de) | Verfahren zur Herstellung integrierter Vorrichtungen in Silizium- und siliziumfreien Substraten mittels Waferbonding | |
| DE10137369A1 (de) | Halbleitersubstrat, Feldeffekt-Transistor, Verfahren zur Bildung einer SiGe-Schicht und Verfahren zur Bildung einer gespannten Si-Schicht unter Verwendung derselben, und Verfahren zur Herstellung eines Feldeffekt-Transistors | |
| DE69204794T2 (de) | Verfahren zur Züchtung von heteroepitaktischen Schichten. | |
| DE112019003987T5 (de) | VERFAHREN ZUR HERSTELLUNG EINES GaN-LAMINATSUBSTRATS | |
| EP1456872A1 (de) | Verfahren zum abscheiden von iii-v-halbleiterschichten auf einem nicht-iii-v-substrat | |
| DE69218896T2 (de) | Verfahren zur Herstellung eines Josephson-Übergangselements mit Schwach-Kopplung aus künstlichen Korngrenzen | |
| DE112021003487B4 (de) | Freistehendes Substrat für epitaktisches Kristallwachstum und dessen Verwendung in einem funktionellen Bauelement | |
| DE69212670T2 (de) | Supraleitende oxydische Dünnschicht mit lokal unterschiedlichen Kristallorientierungen und ein Verfahren zu deren Herstellung | |
| DE69315114T2 (de) | Epitaxie auf einem Substrat | |
| DE69020331T2 (de) | Halbleiteranordnung, die auf einem Siliziumsubstrat oder auf einer Siliziumschicht gebildet wird, und Verfahren zu deren Herstellung. | |
| DE112006002430T5 (de) | Verfahren zur Herstellung von Super-Gittern unter Verwendung von abwechselnden Hoch und Niedrig-Temperatur-Schichten zum Sperren von parasitären Strompfaden | |
| DE10260937A1 (de) | Strahlungssemittierender Halbleiterkörper und Verfahren zu dessen Herstellung | |
| DE112005002838T5 (de) | Halbleiterstapelstruktur auf Basis von Galliumnitrid, Verfahren zu dessen Herstellung, Halbleitervorrichtung auf Basis von Galliumnitrid und Lampe unter Verwendung der Vorrichtung | |
| DE69207503T2 (de) | Einkristall einer Halbleiterverbindung | |
| WO1999014812A1 (de) | Verfahren zum herstellen eines substrates als träger für eine, insbesondere supraleitende, funktionsschicht sowie einer struktur mit einem supraleiter | |
| EP1425784A1 (de) | Verfahren zur herstellung von halbleiterschichten auf iii-v-nitridhalbleiter-basis | |
| DE112018003360B4 (de) | SiC-EPITAXIEWAFER UND VERFAHREN ZUR HERSTELLUNG DESSELBEN |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition | ||
| 8320 | Willingness to grant licences declared (paragraph 23) | ||
| 8339 | Ceased/non-payment of the annual fee |