DE4031136A1 - Fehlersimulationsverfahren - Google Patents

Fehlersimulationsverfahren

Info

Publication number
DE4031136A1
DE4031136A1 DE4031136A DE4031136A DE4031136A1 DE 4031136 A1 DE4031136 A1 DE 4031136A1 DE 4031136 A DE4031136 A DE 4031136A DE 4031136 A DE4031136 A DE 4031136A DE 4031136 A1 DE4031136 A1 DE 4031136A1
Authority
DE
Germany
Prior art keywords
logic
gate
error
data
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE4031136A
Other languages
German (de)
English (en)
Other versions
DE4031136C2 (enExample
Inventor
Masahiko Nagai
Hiroo Watai
Takaharu Nagumo
Kaoru Moriwaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE4031136A1 publication Critical patent/DE4031136A1/de
Application granted granted Critical
Publication of DE4031136C2 publication Critical patent/DE4031136C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
DE4031136A 1989-10-02 1990-10-02 Fehlersimulationsverfahren Granted DE4031136A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1257236A JPH03118488A (ja) 1989-10-02 1989-10-02 故障シミュレーション方式

Publications (2)

Publication Number Publication Date
DE4031136A1 true DE4031136A1 (de) 1991-04-11
DE4031136C2 DE4031136C2 (enExample) 1993-07-01

Family

ID=17303576

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4031136A Granted DE4031136A1 (de) 1989-10-02 1990-10-02 Fehlersimulationsverfahren

Country Status (3)

Country Link
US (1) US5184308A (enExample)
JP (1) JPH03118488A (enExample)
DE (1) DE4031136A1 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9106758D0 (en) * 1991-03-28 1991-05-15 Genrad Ltd A system for determining the operations of an integrated circuit and processor for use therein
DE69225527T2 (de) * 1991-04-11 1998-09-10 Hewlett Packard Co Verfahren und System zur automatischen Bestimmung der logischen Funktion einer Schaltung
JP2781081B2 (ja) * 1991-06-12 1998-07-30 株式会社日立製作所 並列演算機構による論理演算方法
JPH0546697A (ja) * 1991-08-14 1993-02-26 Nec Corp 論理シミユレータ
US5884065A (en) * 1992-01-10 1999-03-16 Nec Corporation Logic circuit apparatus and method for sequentially performing one of a fault-free simulation and a fault simulation through various levels of a logic circuit
US5475624A (en) * 1992-04-30 1995-12-12 Schlumberger Technologies, Inc. Test generation by environment emulation
JPH06194415A (ja) * 1992-09-30 1994-07-15 American Teleph & Telegr Co <Att> 論理回路の試験方法とその装置
US5633813A (en) * 1994-05-04 1997-05-27 Srinivasan; Seshan R. Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits
US5548715A (en) * 1994-06-10 1996-08-20 International Business Machines Corporation Analysis of untestable faults using discrete node sets
US5668816A (en) * 1996-08-19 1997-09-16 International Business Machines Corporation Method and apparatus for injecting errors into an array built-in self-test
US6625770B1 (en) * 2000-06-20 2003-09-23 Lsi Logic Corporation Method of automatically generating schematic and waveform diagrams for relevant logic cells of a circuit using input signal predictors and transition times
US6961887B1 (en) 2001-10-09 2005-11-01 The United States Of America As Represented By The Secretary Of The Navy Streamlined LASAR-to-L200 post-processing for CASS
US20090048708A1 (en) 2007-08-15 2009-02-19 Deline Jonathan E Fuel dispenser
US7870441B2 (en) * 2008-03-18 2011-01-11 International Business Machines Corporation Determining an underlying cause for errors detected in a data processing system
US9032266B2 (en) * 2011-06-28 2015-05-12 Terence Wai-kwok Chan Multithreaded, mixed-HDL/ESL concurrent fault simulator for large-scale integrated circuit designs
US10346273B2 (en) * 2017-09-22 2019-07-09 Analog Devices Global Unlimited Company Automated analog fault injection
CN107861005B (zh) * 2017-11-10 2020-09-29 北京润科通用技术有限公司 一种供电故障模拟装置及供电故障模拟方法
US10969429B1 (en) * 2019-08-13 2021-04-06 Cadence Design Systems, Inc. System and method for debugging in concurrent fault simulation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3221819A1 (de) * 1982-06-09 1984-02-23 Siemens AG, 1000 Berlin und 8000 München Vorrichtung zur simulation eines schaltwerks mit hilfe eines rechners

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0668756B2 (ja) * 1985-04-19 1994-08-31 株式会社日立製作所 回路自動変換方法
JPS62221745A (ja) * 1986-03-24 1987-09-29 Hitachi Ltd 論理回路シミユレ−シヨン方法
US4815016A (en) * 1986-07-24 1989-03-21 Unisys Corp. High speed logical circuit simulator
US4996659A (en) * 1986-08-20 1991-02-26 Hitachi, Ltd. Method of diagnosing integrated logic circuit
US4791578A (en) * 1986-12-30 1988-12-13 Eta Systems, Inc. Logic gate system design
JP2583949B2 (ja) * 1988-03-10 1997-02-19 松下電器産業株式会社 論理シミュレーション方法と論理シミュレーション装置
US4954953A (en) * 1988-04-07 1990-09-04 Vlsi Technology, Inc. Machine process for converting one representation of an electronic integrated circuit into another representation
US4937765A (en) * 1988-07-29 1990-06-26 Mentor Graphics Corporation Method and apparatus for estimating fault coverage

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3221819A1 (de) * 1982-06-09 1984-02-23 Siemens AG, 1000 Berlin und 8000 München Vorrichtung zur simulation eines schaltwerks mit hilfe eines rechners

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DE-Z.: messen + prüfen/automatik, Mai 1976, Jg. 12, H. 5, S. 268-277 *
US-Z.: IEEE Transactions on Computer-Aided Design, Vol. 7, No. 12, December 1988, S. 1250-1260 *

Also Published As

Publication number Publication date
JPH03118488A (ja) 1991-05-21
US5184308A (en) 1993-02-02
DE4031136C2 (enExample) 1993-07-01

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee