DE4006158A1 - Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel - Google Patents

Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel

Info

Publication number
DE4006158A1
DE4006158A1 DE4006158A DE4006158A DE4006158A1 DE 4006158 A1 DE4006158 A1 DE 4006158A1 DE 4006158 A DE4006158 A DE 4006158A DE 4006158 A DE4006158 A DE 4006158A DE 4006158 A1 DE4006158 A1 DE 4006158A1
Authority
DE
Germany
Prior art keywords
layer
silicon
doping
trench
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE4006158A
Other languages
German (de)
English (en)
Other versions
DE4006158C2 (enExample
Inventor
Holger Dr Ing Vogt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority to DE4006158A priority Critical patent/DE4006158A1/de
Priority to DE19904042334 priority patent/DE4042334C2/de
Priority to PCT/DE1991/000162 priority patent/WO1991013463A1/de
Priority to JP3504178A priority patent/JPH07105440B2/ja
Priority to DE59103366T priority patent/DE59103366D1/de
Priority to EP91904136A priority patent/EP0517727B1/de
Priority to DE19914127925 priority patent/DE4127925C2/de
Publication of DE4006158A1 publication Critical patent/DE4006158A1/de
Application granted granted Critical
Publication of DE4006158C2 publication Critical patent/DE4006158C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
DE4006158A 1990-02-27 1990-02-27 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel Granted DE4006158A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE4006158A DE4006158A1 (de) 1990-02-27 1990-02-27 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel
DE19904042334 DE4042334C2 (de) 1990-02-27 1990-02-27 Verfahren zum Erzeugen einer isolierten, einkristallinen Siliziuminsel
PCT/DE1991/000162 WO1991013463A1 (de) 1990-02-27 1991-02-26 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel
JP3504178A JPH07105440B2 (ja) 1990-02-27 1991-02-26 絶縁された単結晶シリコンアイランドの製法
DE59103366T DE59103366D1 (de) 1990-02-27 1991-02-26 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel.
EP91904136A EP0517727B1 (de) 1990-02-27 1991-02-26 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel
DE19914127925 DE4127925C2 (de) 1990-02-27 1991-08-23 Verfahren zum Erzeugen einer isolierten, einkristallinen Siliziuminsel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4006158A DE4006158A1 (de) 1990-02-27 1990-02-27 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel

Publications (2)

Publication Number Publication Date
DE4006158A1 true DE4006158A1 (de) 1991-09-12
DE4006158C2 DE4006158C2 (enExample) 1992-03-12

Family

ID=6401063

Family Applications (2)

Application Number Title Priority Date Filing Date
DE4006158A Granted DE4006158A1 (de) 1990-02-27 1990-02-27 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel
DE59103366T Expired - Fee Related DE59103366D1 (de) 1990-02-27 1991-02-26 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE59103366T Expired - Fee Related DE59103366D1 (de) 1990-02-27 1991-02-26 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel.

Country Status (4)

Country Link
EP (1) EP0517727B1 (enExample)
JP (1) JPH07105440B2 (enExample)
DE (2) DE4006158A1 (enExample)
WO (1) WO1991013463A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4201910C2 (de) * 1991-11-29 1995-05-11 Fraunhofer Ges Forschung Verfahren zum Herstellen einer Halbleiterstruktur für eine integrierte Leistungsschaltung mit einem vertikalen Leistungsbauelement
US5457068A (en) * 1992-11-30 1995-10-10 Texas Instruments Incorporated Monolithic integration of microwave silicon devices and low loss transmission lines
GB2327146A (en) * 1997-07-10 1999-01-13 Ericsson Telefon Ab L M Thermal insulation of integrated circuit components
DE102010028044B4 (de) * 2010-04-21 2017-08-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Drucksensor und Verfahren zu dessen Herstellung
DE102017212437B3 (de) 2017-07-20 2018-12-20 Infineon Technologies Ag Verfahren zum Herstellen einer vergrabenen Hohlraumstruktur

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2451861A1 (de) * 1973-11-02 1975-05-15 Hitachi Ltd Integrierte halbleiterschaltungsbauelemente
US3897274A (en) * 1971-06-01 1975-07-29 Texas Instruments Inc Method of fabricating dielectrically isolated semiconductor structures
EP0167437B1 (fr) * 1984-06-14 1988-12-28 Commissariat A L'energie Atomique Procédé d'autopositionnement d'un oxyde de champ localisé par rapport à une tranchée d'isolement
EP0325161A2 (en) * 1988-01-21 1989-07-26 Fujitsu Limited Semiconductor device having trench isolation
EP0328331A2 (en) * 1988-02-08 1989-08-16 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment
JPS62266875A (ja) * 1986-05-14 1987-11-19 Nippon Denso Co Ltd 半導体圧力センサ
JPS6467935A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Manufacture of semiconductor device
KR910009318B1 (ko) * 1987-09-08 1991-11-09 미쓰비시 뎅끼 가부시기가이샤 반도체 장치의 제조 및 고내압 파묻음 절연막 형성방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897274A (en) * 1971-06-01 1975-07-29 Texas Instruments Inc Method of fabricating dielectrically isolated semiconductor structures
DE2451861A1 (de) * 1973-11-02 1975-05-15 Hitachi Ltd Integrierte halbleiterschaltungsbauelemente
EP0167437B1 (fr) * 1984-06-14 1988-12-28 Commissariat A L'energie Atomique Procédé d'autopositionnement d'un oxyde de champ localisé par rapport à une tranchée d'isolement
EP0325161A2 (en) * 1988-01-21 1989-07-26 Fujitsu Limited Semiconductor device having trench isolation
EP0328331A2 (en) * 1988-02-08 1989-08-16 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Electronics, 26.11.87, S. 127-129 *

Also Published As

Publication number Publication date
DE59103366D1 (de) 1994-12-01
DE4006158C2 (enExample) 1992-03-12
JPH07105440B2 (ja) 1995-11-13
EP0517727A1 (de) 1992-12-16
WO1991013463A1 (de) 1991-09-05
EP0517727B1 (de) 1994-10-26
JPH05506749A (ja) 1993-09-30

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