DE3940200A1 - Verfahren zum herstellen eines gaas-fets mit kanaleingrenzungsschichten - Google Patents

Verfahren zum herstellen eines gaas-fets mit kanaleingrenzungsschichten

Info

Publication number
DE3940200A1
DE3940200A1 DE3940200A DE3940200A DE3940200A1 DE 3940200 A1 DE3940200 A1 DE 3940200A1 DE 3940200 A DE3940200 A DE 3940200A DE 3940200 A DE3940200 A DE 3940200A DE 3940200 A1 DE3940200 A1 DE 3940200A1
Authority
DE
Germany
Prior art keywords
producing
channel construction
gaas fet
construction layers
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3940200A
Other languages
English (en)
Other versions
DE3940200C2 (de
Inventor
Arthur Eugent Geissberger
Robert Allen Sadler
Gregory E Menk
Matthew Lee Balzan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Solutions GmbH
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of DE3940200A1 publication Critical patent/DE3940200A1/de
Application granted granted Critical
Publication of DE3940200C2 publication Critical patent/DE3940200C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/015—Capping layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/084—Ion implantation of compound devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
DE3940200A 1988-12-06 1989-12-05 Verfahren zum Herstellen eines GaAs-FETs Expired - Fee Related DE3940200C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/280,780 US4962050A (en) 1988-12-06 1988-12-06 GaAs FET manufacturing process employing channel confining layers

Publications (2)

Publication Number Publication Date
DE3940200A1 true DE3940200A1 (de) 1990-06-07
DE3940200C2 DE3940200C2 (de) 2002-10-02

Family

ID=23074618

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3940200A Expired - Fee Related DE3940200C2 (de) 1988-12-06 1989-12-05 Verfahren zum Herstellen eines GaAs-FETs

Country Status (4)

Country Link
US (1) US4962050A (de)
JP (1) JP3040786B2 (de)
DE (1) DE3940200C2 (de)
GB (1) GB2225898B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2817217B2 (ja) * 1989-06-30 1998-10-30 日本電気株式会社 金属・半導体接合を有する半導体装置およびその製造方法
US5309006A (en) * 1991-11-05 1994-05-03 Itt Corporation FET crossbar switch device particularly useful for microwave applications
US5411902A (en) * 1994-06-06 1995-05-02 The United States Of America As Represented By The Secretary Of The Air Force Process for improving gallium arsenide field effect transistor performance using an aluminum arsenide or an aluminum gallium arsenide buffer layer
JP3169775B2 (ja) * 1994-08-29 2001-05-28 株式会社日立製作所 半導体回路、スイッチ及びそれを用いた通信機
US20080026545A1 (en) 2006-07-28 2008-01-31 Paul Cooke Integrated devices on a common compound semiconductor III-V wafer
US7700423B2 (en) * 2006-07-28 2010-04-20 Iqe Rf, Llc Process for manufacturing epitaxial wafers for integrated devices on a common compound semiconductor III-V wafer
CN112380659A (zh) * 2020-11-11 2021-02-19 天津大学 基于新型电阻模型的GaN HEMT等效电路拓扑结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59207667A (ja) * 1983-05-11 1984-11-24 Hitachi Ltd 半導体装置
JPS60189268A (ja) * 1984-03-08 1985-09-26 Fujitsu Ltd 半導体装置
JPH088350B2 (ja) * 1985-04-08 1996-01-29 日本電気株式会社 半導体装置
EP0237029A3 (de) * 1986-03-10 1988-01-27 Nec Corporation Feldeffektanordnung mit Heteroübergang, die bei einer hohen Stromstärke funktioniert und mit hoher Durchschlagspannung
FR2600821B1 (fr) * 1986-06-30 1988-12-30 Thomson Csf Dispositif semi-conducteur a heterojonction et double canal, son application a un transistor a effet de champ, et son application a un dispositif de transductance negative
US4792531A (en) * 1987-10-05 1988-12-20 Menlo Industries, Inc. Self-aligned gate process

Also Published As

Publication number Publication date
GB2225898A (en) 1990-06-13
US4962050A (en) 1990-10-09
DE3940200C2 (de) 2002-10-02
JPH02201934A (ja) 1990-08-10
GB8926928D0 (en) 1990-01-17
JP3040786B2 (ja) 2000-05-15
GB2225898B (en) 1992-09-09

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8127 New person/name/address of the applicant

Owner name: TYCO ELECTRONICS LOGISTICS AG, STEINACH, CH

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee