DE3938153A1 - Mikroprozessor - Google Patents

Mikroprozessor

Info

Publication number
DE3938153A1
DE3938153A1 DE19893938153 DE3938153A DE3938153A1 DE 3938153 A1 DE3938153 A1 DE 3938153A1 DE 19893938153 DE19893938153 DE 19893938153 DE 3938153 A DE3938153 A DE 3938153A DE 3938153 A1 DE3938153 A1 DE 3938153A1
Authority
DE
Germany
Prior art keywords
test data
memory
error bit
data
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19893938153
Other languages
German (de)
English (en)
Other versions
DE3938153C2 (enrdf_load_stackoverflow
Inventor
Takesi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3938153A1 publication Critical patent/DE3938153A1/de
Application granted granted Critical
Publication of DE3938153C2 publication Critical patent/DE3938153C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE19893938153 1989-04-18 1989-11-16 Mikroprozessor Granted DE3938153A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1096220A JPH02276099A (ja) 1989-04-18 1989-04-18 マイクロプロセッサ

Publications (2)

Publication Number Publication Date
DE3938153A1 true DE3938153A1 (de) 1990-10-25
DE3938153C2 DE3938153C2 (enrdf_load_stackoverflow) 1991-11-21

Family

ID=14159155

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19893938153 Granted DE3938153A1 (de) 1989-04-18 1989-11-16 Mikroprozessor

Country Status (3)

Country Link
JP (1) JPH02276099A (enrdf_load_stackoverflow)
DE (1) DE3938153A1 (enrdf_load_stackoverflow)
FR (1) FR2646003B1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102968354A (zh) * 2012-11-13 2013-03-13 浪潮电子信息产业股份有限公司 一种基于Intel Brickland-EX平台的同频锁步模式的自动切换方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006040900A1 (ja) * 2004-10-14 2006-04-20 Advantest Corporation 誤り訂正符号が付加されたデータ列を記憶する被試験メモリを試験する試験装置及び試験方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62120699A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd 半導体記憶装置
DE3634352A1 (de) * 1986-10-08 1988-04-21 Siemens Ag Verfahren und anordnung zum testen von mega-bit-speicherbausteinen mit beliebigen testmustern im multi-bit-testmodus
DE3603926C2 (enrdf_load_stackoverflow) * 1985-02-07 1988-12-01 Mitsubishi Denki K.K., Tokio/Tokyo, Jp

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58205993A (ja) * 1982-05-25 1983-12-01 Fujitsu Ltd Ｌｓｉ内蔵メモリのスキヤンテスト方法
CA1203631A (en) * 1982-11-26 1986-04-22 John L. Judge Detecting improper operation of a digital data processing apparatus
JPS61196341A (ja) * 1985-02-27 1986-08-30 Fuji Electric Co Ltd メモリの誤り訂正方式

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3603926C2 (enrdf_load_stackoverflow) * 1985-02-07 1988-12-01 Mitsubishi Denki K.K., Tokio/Tokyo, Jp
JPS62120699A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd 半導体記憶装置
DE3634352A1 (de) * 1986-10-08 1988-04-21 Siemens Ag Verfahren und anordnung zum testen von mega-bit-speicherbausteinen mit beliebigen testmustern im multi-bit-testmodus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Kinoshita Kozo und Saluja Kewal K., Built-In Testing of Memory Using an On-Chip Compact Testing Scheme, in: IEEE Transactions on ComputersVol. C-35, No. 10, Oktober 1986, S. 862-870 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102968354A (zh) * 2012-11-13 2013-03-13 浪潮电子信息产业股份有限公司 一种基于Intel Brickland-EX平台的同频锁步模式的自动切换方法

Also Published As

Publication number Publication date
JPH02276099A (ja) 1990-11-09
DE3938153C2 (enrdf_load_stackoverflow) 1991-11-21
FR2646003B1 (fr) 1994-09-16
FR2646003A1 (fr) 1990-10-19

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G11C 29/00

D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licenses declared (paragraph 23)
8339 Ceased/non-payment of the annual fee