DE3878037T2 - Vertikaler mosfet mit einer spannungsregler-diode, die sich nicht tief unter der oberflaeche befindet. - Google Patents

Vertikaler mosfet mit einer spannungsregler-diode, die sich nicht tief unter der oberflaeche befindet.

Info

Publication number
DE3878037T2
DE3878037T2 DE8888107525T DE3878037T DE3878037T2 DE 3878037 T2 DE3878037 T2 DE 3878037T2 DE 8888107525 T DE8888107525 T DE 8888107525T DE 3878037 T DE3878037 T DE 3878037T DE 3878037 T2 DE3878037 T2 DE 3878037T2
Authority
DE
Germany
Prior art keywords
voltage regulator
regulator diode
vertical mosfet
deep under
deep
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888107525T
Other languages
English (en)
Other versions
DE3878037D1 (de
Inventor
Teruyoshi Mihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Publication of DE3878037D1 publication Critical patent/DE3878037D1/de
Application granted granted Critical
Publication of DE3878037T2 publication Critical patent/DE3878037T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
DE8888107525T 1987-05-29 1988-05-10 Vertikaler mosfet mit einer spannungsregler-diode, die sich nicht tief unter der oberflaeche befindet. Expired - Fee Related DE3878037T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62133960A JP2724146B2 (ja) 1987-05-29 1987-05-29 縦形mosfet

Publications (2)

Publication Number Publication Date
DE3878037D1 DE3878037D1 (de) 1993-03-18
DE3878037T2 true DE3878037T2 (de) 1993-05-19

Family

ID=15117103

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888107525T Expired - Fee Related DE3878037T2 (de) 1987-05-29 1988-05-10 Vertikaler mosfet mit einer spannungsregler-diode, die sich nicht tief unter der oberflaeche befindet.

Country Status (4)

Country Link
US (1) US4931846A (de)
EP (1) EP0292782B1 (de)
JP (1) JP2724146B2 (de)
DE (1) DE3878037T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01117363A (ja) * 1987-10-30 1989-05-10 Nec Corp 縦型絶縁ゲート電界効果トランジスタ
US5119162A (en) * 1989-02-10 1992-06-02 Texas Instruments Incorporated Integrated power DMOS circuit with protection diode
JPH03238871A (ja) * 1990-02-15 1991-10-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0521792A (ja) * 1991-07-10 1993-01-29 Mels Corp ゼロクロス・スイツチング素子
US5289028A (en) * 1991-11-04 1994-02-22 Motorola, Inc. High power semiconductor device with integral on-state voltage detection structure
GB9216599D0 (en) * 1992-08-05 1992-09-16 Philips Electronics Uk Ltd A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device
KR950006352B1 (ko) * 1992-12-31 1995-06-14 삼성전자주식회사 정류성 전송 게이트와 그 응용회로
JP3216743B2 (ja) * 1993-04-22 2001-10-09 富士電機株式会社 トランジスタ用保護ダイオード
DE69326543T2 (de) * 1993-04-28 2000-01-05 Cons Ric Microelettronica Monolithisch integrierte Struktur einer elektronischen Vorrichtung mit einer bestimmten unidirektionalen Konduktionsschwellenspannung
US5701023A (en) * 1994-08-03 1997-12-23 National Semiconductor Corporation Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness
EP0765025A3 (de) * 1995-09-21 1998-12-30 Siemens Aktiengesellschaft Anlaufschaltung und Halbleiterkörper für eine solche Anlaufschaltung
WO1997016853A1 (en) * 1995-11-02 1997-05-09 National Semiconductor Corporation Insulated gate semiconductor devices with implants for improved ruggedness
JP2007081436A (ja) * 1996-10-18 2007-03-29 Hitachi Ltd 半導体装置及びそれを使った電力変換装置
US6121089A (en) * 1997-10-17 2000-09-19 Intersil Corporation Methods of forming power semiconductor devices having merged split-well body regions therein
US6172383B1 (en) 1997-12-31 2001-01-09 Siliconix Incorporated Power MOSFET having voltage-clamped gate
US6268242B1 (en) * 1997-12-31 2001-07-31 Richard K. Williams Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact
JP5134746B2 (ja) * 2001-09-20 2013-01-30 新電元工業株式会社 電界効果トランジスタの製造方法
US7221010B2 (en) * 2002-12-20 2007-05-22 Cree, Inc. Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
JP2004214575A (ja) * 2003-01-09 2004-07-29 Matsushita Electric Ind Co Ltd 半導体装置
JP4892172B2 (ja) * 2003-08-04 2012-03-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN101882583A (zh) 2005-04-06 2010-11-10 飞兆半导体公司 沟栅场效应晶体管及其形成方法
WO2014203317A1 (ja) * 2013-06-17 2014-12-24 株式会社日立製作所 半導体装置およびその製造方法、並びに電力変換装置
CN109103258A (zh) * 2018-08-21 2018-12-28 电子科技大学 一种槽栅dmos器件

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2034686B (en) * 1978-11-06 1983-05-05 Philips Electronic Associated Master replicating tool
JPS60196975A (ja) * 1984-08-24 1985-10-05 Nissan Motor Co Ltd 縦型mosfet
JPS5998557A (ja) * 1982-11-27 1984-06-06 Nissan Motor Co Ltd Mosトランジスタ
JPS59214263A (ja) * 1983-05-20 1984-12-04 Toshiba Corp 二重拡散形絶縁ゲ−ト電界効果トランジスタ
JPS6019695A (ja) * 1983-07-13 1985-01-31 株式会社日立製作所 巻上ロ−プの過負荷防止装置
JP2572210B2 (ja) * 1984-11-20 1997-01-16 三菱電機株式会社 縦型パワ−mos電界効果型半導体装置

Also Published As

Publication number Publication date
DE3878037D1 (de) 1993-03-18
JPS63299279A (ja) 1988-12-06
EP0292782A2 (de) 1988-11-30
US4931846A (en) 1990-06-05
EP0292782A3 (en) 1990-02-07
JP2724146B2 (ja) 1998-03-09
EP0292782B1 (de) 1993-02-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee