DE3875985T2 - Logische schaltung mit feldeffekttransistor, der eine verbindung mit gleichrichtender charakteristik zwischen gatter und quelle aufweist. - Google Patents

Logische schaltung mit feldeffekttransistor, der eine verbindung mit gleichrichtender charakteristik zwischen gatter und quelle aufweist.

Info

Publication number
DE3875985T2
DE3875985T2 DE8888301948T DE3875985T DE3875985T2 DE 3875985 T2 DE3875985 T2 DE 3875985T2 DE 8888301948 T DE8888301948 T DE 8888301948T DE 3875985 T DE3875985 T DE 3875985T DE 3875985 T2 DE3875985 T2 DE 3875985T2
Authority
DE
Germany
Prior art keywords
gate
terminal
voltage
field effect
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888301948T
Other languages
German (de)
English (en)
Other versions
DE3875985D1 (de
Inventor
Yuu Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3875985D1 publication Critical patent/DE3875985D1/de
Application granted granted Critical
Publication of DE3875985T2 publication Critical patent/DE3875985T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/16—Conversion to or from representation by pulses the pulses having three levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE8888301948T 1987-03-11 1988-03-07 Logische schaltung mit feldeffekttransistor, der eine verbindung mit gleichrichtender charakteristik zwischen gatter und quelle aufweist. Expired - Fee Related DE3875985T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5395287 1987-03-11

Publications (2)

Publication Number Publication Date
DE3875985D1 DE3875985D1 (de) 1992-12-24
DE3875985T2 true DE3875985T2 (de) 1993-04-01

Family

ID=12957054

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888301948T Expired - Fee Related DE3875985T2 (de) 1987-03-11 1988-03-07 Logische schaltung mit feldeffekttransistor, der eine verbindung mit gleichrichtender charakteristik zwischen gatter und quelle aufweist.

Country Status (5)

Country Link
US (1) US4900953A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0282249B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS64817A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR900008803B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3875985T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5147470A (en) * 1990-12-25 1992-09-15 Hitachi Metals, Ltd. High strength lead frame material and method of producing the same
JP3429821B2 (ja) * 1992-11-04 2003-07-28 テキサス インスツルメンツ インコーポレイテツド 多機能共鳴トンネリング論理ゲート
JP2002217416A (ja) * 2001-01-16 2002-08-02 Hitachi Ltd 半導体装置
US7180762B2 (en) * 2004-08-23 2007-02-20 International Rectifier Corporation Cascoded rectifier
US7408399B2 (en) * 2005-06-27 2008-08-05 International Rectifier Corporation Active driving of normally on, normally off cascoded configuration devices through asymmetrical CMOS
DE102013114547B4 (de) 2013-01-18 2020-01-16 Schott Ag TO-Gehäuse

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4048518A (en) * 1976-02-10 1977-09-13 Intel Corporation MOS buffer circuit
JPS58114528A (ja) * 1981-12-26 1983-07-07 Toshiba Corp ＧａＡｓ論理集積回路
US4743782A (en) * 1984-11-09 1988-05-10 Honeywell Inc. GaAs level-shift logic interface circuit
JPS6297427A (ja) * 1985-08-09 1987-05-06 Sumitomo Electric Ind Ltd 半導体装置

Also Published As

Publication number Publication date
EP0282249A3 (en) 1989-11-08
US4900953A (en) 1990-02-13
EP0282249A2 (en) 1988-09-14
DE3875985D1 (de) 1992-12-24
JPH0543216B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-07-01
KR900008803B1 (en) 1990-11-29
JPS64817A (en) 1989-01-05
KR880012012A (ko) 1988-10-31
EP0282249B1 (en) 1992-11-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee