DE3874261D1 - Einrichtung zur erzeugung von signalen zur zeitverschiebungskompensation. - Google Patents

Einrichtung zur erzeugung von signalen zur zeitverschiebungskompensation.

Info

Publication number
DE3874261D1
DE3874261D1 DE8888111128T DE3874261T DE3874261D1 DE 3874261 D1 DE3874261 D1 DE 3874261D1 DE 8888111128 T DE8888111128 T DE 8888111128T DE 3874261 T DE3874261 T DE 3874261T DE 3874261 D1 DE3874261 D1 DE 3874261D1
Authority
DE
Germany
Prior art keywords
time shift
generating signals
shift compensation
compensation
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888111128T
Other languages
English (en)
Other versions
DE3874261T2 (de
Inventor
Hans J Greub
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC.,
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of DE3874261D1 publication Critical patent/DE3874261D1/de
Application granted granted Critical
Publication of DE3874261T2 publication Critical patent/DE3874261T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H03K2005/00104—Avoiding variations of delay using feedback, e.g. controlled by a PLL using a reference signal, e.g. a reference clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00182—Layout of the delay element using bipolar transistors using constant current sources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00228—Layout of the delay element having complementary input and output signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE8888111128T 1987-09-08 1988-07-12 Einrichtung zur erzeugung von signalen zur zeitverschiebungskompensation. Expired - Fee Related DE3874261T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/093,930 US4833695A (en) 1987-09-08 1987-09-08 Apparatus for skew compensating signals

Publications (2)

Publication Number Publication Date
DE3874261D1 true DE3874261D1 (de) 1992-10-08
DE3874261T2 DE3874261T2 (de) 1993-04-01

Family

ID=22241762

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888111128T Expired - Fee Related DE3874261T2 (de) 1987-09-08 1988-07-12 Einrichtung zur erzeugung von signalen zur zeitverschiebungskompensation.

Country Status (4)

Country Link
US (1) US4833695A (de)
EP (1) EP0306662B1 (de)
JP (1) JPH0642664B2 (de)
DE (1) DE3874261T2 (de)

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US5455831A (en) * 1992-02-20 1995-10-03 International Business Machines Corporation Frame group transmission and reception for parallel/serial buses
US5257144A (en) * 1992-03-06 1993-10-26 Grumman Aerospace Corporation Synchronization and automatic resynchronization of multiple incremental recorders
FR2689339B1 (fr) * 1992-03-24 1996-12-13 Bull Sa Procede et dispositif de reglage de retard a plusieurs gammes.
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US5191301A (en) * 1992-05-12 1993-03-02 International Business Machines Corporation Integrated differential voltage controlled ring oscillator
US5533188A (en) * 1992-10-19 1996-07-02 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Fault-tolerant processing system
DE69323692T2 (de) * 1992-11-02 1999-09-16 Koninkl Philips Electronics Nv Optimale Entwurfmethode für synchrone digitale Schaltkreise durch Hertakten und selektives Setzen von Kipp-schaltungen
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US5717729A (en) * 1994-06-30 1998-02-10 Digital Equipment Corporation Low skew remote absolute delay regulator chip
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US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6002280A (en) * 1997-04-24 1999-12-14 Mitsubishi Semiconductor America, Inc. Adaptable output phase delay compensation circuit and method thereof
US6247138B1 (en) 1997-06-12 2001-06-12 Fujitsu Limited Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
DE19736857C1 (de) * 1997-08-23 1999-01-07 Philips Patentverwaltung Ringoszillator
JP2970845B2 (ja) 1997-09-03 1999-11-02 日本電気株式会社 ディジタルｄｌｌ回路
KR100264077B1 (ko) * 1997-11-21 2000-08-16 김영환 반도체 소자의 클럭보상장치
JPH11274904A (ja) * 1998-03-26 1999-10-08 Sanyo Electric Co Ltd 遅延回路
JP2000244286A (ja) * 1999-02-22 2000-09-08 Mitsubishi Electric Corp 電圧制御発振装置
US6208212B1 (en) 1999-03-11 2001-03-27 Ericsson Inc. Delay cell with controlled output amplitude
JP2001338985A (ja) * 1999-09-20 2001-12-07 Matsushita Electric Ind Co Ltd クロック回路及びその設計方法
JP3623421B2 (ja) * 2000-01-26 2005-02-23 Ｎｅｃエレクトロニクス株式会社 電圧制御発振器
US7333516B1 (en) 2000-07-20 2008-02-19 Silicon Graphics, Inc. Interface for synchronous data transfer between domains clocked at different frequencies
US6518812B1 (en) 2000-07-20 2003-02-11 Silicon Graphics, Inc. Discrete delay line system and method
US6839856B1 (en) 2000-07-20 2005-01-04 Silicon Graphics, Inc. Method and circuit for reliable data capture in the presence of bus-master changeovers
US6496048B1 (en) 2000-07-20 2002-12-17 Silicon Graphics, Inc. System and method for accurate adjustment of discrete integrated circuit delay lines
US6441666B1 (en) 2000-07-20 2002-08-27 Silicon Graphics, Inc. System and method for generating clock signals
US6781984B1 (en) * 2000-08-30 2004-08-24 Ciena Corporation Techniques and architectures for implementing a data skew equalizer for data alignment in a distributed system
DE10147121B4 (de) * 2000-09-29 2004-06-17 Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto Schaltung zum Aufteilen der Fein- und Grob-Verzögerungssteuerung von Verzögerungsleitungen zur Verwendung beim Laden von Verzögerungsdaten
US6650190B2 (en) * 2001-04-11 2003-11-18 International Business Machines Corporation Ring oscillator with adjustable delay
WO2002095943A2 (en) * 2001-05-21 2002-11-28 Vasily Grigorievich Atyunin Programmable self-calibrating vernier and method
DE10135582C1 (de) * 2001-07-20 2003-01-16 Infineon Technologies Ag Justierschaltung und Verfahren zum Abstimmen eines Taktsignals
US6628154B2 (en) * 2001-07-31 2003-09-30 Cypress Semiconductor Corp. Digitally controlled analog delay locked loop (DLL)
FI113113B (fi) * 2001-11-20 2004-02-27 Nokia Corp Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi
US6651230B2 (en) 2001-12-07 2003-11-18 International Business Machines Corporation Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design
US7373561B2 (en) * 2002-10-29 2008-05-13 Broadcom Corporation Integrated packet bit error rate tester for 10G SERDES
US8385188B2 (en) 2002-10-29 2013-02-26 Broadcom Corporation Multi-port, gigabit serdes transceiver capable of automatic fail switchover
US6825707B2 (en) 2003-03-10 2004-11-30 Infineon Technologies Ag Current mode logic (CML) circuit concept for a variable delay element
KR100543925B1 (ko) * 2003-06-27 2006-01-23 주식회사 하이닉스반도체 지연 고정 루프 및 지연 고정 루프에서의 클럭 지연 고정방법
US7430240B2 (en) * 2003-10-29 2008-09-30 Broadcom Corporation Apparatus and method for automatic polarity swap in a communications system
EP1560333A3 (de) * 2004-02-02 2007-06-20 Synthesys Research, Inc. Verfahren und Vorrichtung zur Erzeugung variabler Verzögerung
US7233274B1 (en) 2005-12-20 2007-06-19 Impinj, Inc. Capacitive level shifting for analog signal processing
US7593050B2 (en) * 2006-02-27 2009-09-22 Eastman Kodak Company Delay management circuit for reading out large S/H arrays
US7301410B2 (en) * 2006-03-07 2007-11-27 International Business Machines Corporation Hybrid current-starved phase-interpolation circuit for voltage-controlled devices
JP5034329B2 (ja) * 2006-06-09 2012-09-26 富士通株式会社 デスキュー装置およびデスキュー方法
US8699514B2 (en) 2007-01-12 2014-04-15 Broadcom Corporation Multi-rate MAC to PHY interface
JP2010233180A (ja) * 2009-03-30 2010-10-14 Nippon Telegr & Teleph Corp <Ntt> 可変遅延回路
JP2011003986A (ja) * 2009-06-16 2011-01-06 Toshiba Corp クロック生成装置、クロック生成方法およびデジタル放送受信装置
CN102668378B (zh) * 2009-12-25 2015-01-07 佳能株式会社 信息处理装置和信息处理方法
JP2012029211A (ja) * 2010-07-27 2012-02-09 Fujitsu Ltd タイミング調整回路
JP5717897B2 (ja) * 2014-03-14 2015-05-13 キヤノン株式会社 情報処理装置又は情報処理方法
JP7432567B2 (ja) * 2021-09-21 2024-02-16 アンリツ株式会社 信号発生装置及び信号発生方法

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Also Published As

Publication number Publication date
JPS6472641A (en) 1989-03-17
EP0306662A2 (de) 1989-03-15
EP0306662A3 (en) 1989-08-02
JPH0642664B2 (ja) 1994-06-01
DE3874261T2 (de) 1993-04-01
US4833695A (en) 1989-05-23
EP0306662B1 (de) 1992-09-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ST. CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC.,

8339 Ceased/non-payment of the annual fee