DE3850608D1 - Cache-Speicheranordnung. - Google Patents

Cache-Speicheranordnung.

Info

Publication number
DE3850608D1
DE3850608D1 DE3850608T DE3850608T DE3850608D1 DE 3850608 D1 DE3850608 D1 DE 3850608D1 DE 3850608 T DE3850608 T DE 3850608T DE 3850608 T DE3850608 T DE 3850608T DE 3850608 D1 DE3850608 D1 DE 3850608D1
Authority
DE
Germany
Prior art keywords
cache memory
memory arrangement
arrangement
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850608T
Other languages
English (en)
Other versions
DE3850608T2 (de
Inventor
Kazue Yamaguchi
Hideki Osone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3850608D1 publication Critical patent/DE3850608D1/de
Application granted granted Critical
Publication of DE3850608T2 publication Critical patent/DE3850608T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
DE19883850608 1987-05-18 1988-05-11 Cache-Speicheranordnung. Expired - Fee Related DE3850608T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62120602A JPS63284648A (ja) 1987-05-18 1987-05-18 キャッシュメモリ制御方法

Publications (2)

Publication Number Publication Date
DE3850608D1 true DE3850608D1 (de) 1994-08-18
DE3850608T2 DE3850608T2 (de) 1994-11-24

Family

ID=14790317

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883850608 Expired - Fee Related DE3850608T2 (de) 1987-05-18 1988-05-11 Cache-Speicheranordnung.

Country Status (6)

Country Link
EP (1) EP0292188B1 (de)
JP (1) JPS63284648A (de)
AU (1) AU587935B2 (de)
BR (1) BR8802439A (de)
DE (1) DE3850608T2 (de)
ES (1) ES2056926T3 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0886209B1 (de) * 1991-07-08 2005-03-23 Seiko Epson Corporation RISC-Prozessor mit erweiterbarer Architektur
US5778434A (en) 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
JP3071752B2 (ja) 1998-03-24 2000-07-31 三菱電機株式会社 ブリッジ方法、バスブリッジ及びマルチプロセッサシステム
CN1168025C (zh) * 1999-03-10 2004-09-22 国际商业机器公司 用于多线程处理机的指令高速缓存器
JP4504132B2 (ja) * 2004-07-30 2010-07-14 富士通株式会社 記憶制御装置、中央処理装置、情報処理装置及び記憶制御装置の制御方法
WO2010024071A1 (ja) * 2008-08-25 2010-03-04 日本電気株式会社 キャッシュメモリ、そのシステム、その利用方法及びその利用プログラム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3015013A1 (de) * 1980-04-18 1981-10-22 Grünzweig + Hartmann und Glasfaser AG, 6700 Ludwigshafen Waermedaemmantel fuer einen rohrbogen
JPS588366A (ja) * 1981-07-09 1983-01-18 Toshiba Corp メモリモジユ−ルシステム
US4551799A (en) * 1983-02-28 1985-11-05 Honeywell Information Systems Inc. Verification of real page numbers of stack stored prefetched instructions from instruction cache
JPS615357A (ja) * 1984-06-07 1986-01-11 Fujitsu Ltd デ−タ処理装置

Also Published As

Publication number Publication date
AU1588388A (en) 1988-12-15
JPS63284648A (ja) 1988-11-21
BR8802439A (pt) 1988-12-13
ES2056926T3 (es) 1994-10-16
EP0292188A2 (de) 1988-11-23
JPH0516061B2 (de) 1993-03-03
DE3850608T2 (de) 1994-11-24
EP0292188A3 (en) 1990-09-26
EP0292188B1 (de) 1994-07-13
AU587935B2 (en) 1989-08-31

Similar Documents

Publication Publication Date Title
DE69023568D1 (de) Cache-Speicheranordnung.
DE3887324D1 (de) Speicheranordnung.
DE68923863T2 (de) Ein-/Ausgabecachespeicherung.
IT1215539B (it) Memoria tampone trasparente.
DE3885594T2 (de) Speicherprüfgerät.
DE3869158D1 (de) Speicher-leseschaltung.
DE3783100T2 (de) Festwertspeicheranordnung.
DE3873388T2 (de) Cache-speicher.
DE3881896T2 (de) Gefrieranordnung.
DE3851241T2 (de) Speicheranordnung.
FI885427A (fi) Substituerade hydroxylaminer.
DE3789044D1 (de) Cachespeicherungspriorität.
DE3883064D1 (de) Festwertspeicherschaltung.
DE68924945T2 (de) Pufferspeicheranordnung.
DE3850608D1 (de) Cache-Speicheranordnung.
DE68924860T2 (de) Erweiterte Speicheranordnung.
DE3861543D1 (de) Knickstab-anordnung.
DE3871823T2 (de) Halbleiterspeicheranordnung.
FI893041A (fi) Substituerade azacyklohexylderivat.
DE3854005D1 (de) Speicherzelle.
DE3887862T2 (de) Cache-Speichervorrichtung.
TR23376A (tr) Payplayn hafiza struektuerue
DE68921869D1 (de) Ein-/Ausgabebuscachespeicherung.
DE3853933T2 (de) Unterbrechbares Cache-Laden.
DE3851601D1 (de) Speicheranordnung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee