DE3789044D1 - Cachespeicherungspriorität. - Google Patents

Cachespeicherungspriorität.

Info

Publication number
DE3789044D1
DE3789044D1 DE87308810T DE3789044T DE3789044D1 DE 3789044 D1 DE3789044 D1 DE 3789044D1 DE 87308810 T DE87308810 T DE 87308810T DE 3789044 T DE3789044 T DE 3789044T DE 3789044 D1 DE3789044 D1 DE 3789044D1
Authority
DE
Germany
Prior art keywords
cache priority
cache
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE87308810T
Other languages
English (en)
Inventor
Michael D Taylor
Mehrzad Kasrazadeh
Jeffrey A Thomas
Christopher D Finan
Joseph A Petolino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu IT Holdings Inc
Original Assignee
Amdahl Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amdahl Corp filed Critical Amdahl Corp
Application granted granted Critical
Publication of DE3789044D1 publication Critical patent/DE3789044D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE87308810T 1986-10-17 1987-10-05 Cachespeicherungspriorität. Expired - Lifetime DE3789044D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/920,803 US4722046A (en) 1986-08-27 1986-10-17 Cache storage priority

Publications (1)

Publication Number Publication Date
DE3789044D1 true DE3789044D1 (de) 1994-03-24

Family

ID=25444435

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87308810T Expired - Lifetime DE3789044D1 (de) 1986-10-17 1987-10-05 Cachespeicherungspriorität.

Country Status (6)

Country Link
US (1) US4722046A (de)
EP (1) EP0265108B1 (de)
JP (1) JPS63191253A (de)
AU (1) AU597117B2 (de)
CA (1) CA1286782C (de)
DE (1) DE3789044D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
JPH06100968B2 (ja) * 1986-03-25 1994-12-12 日本電気株式会社 情報処理装置
US4888689A (en) * 1986-10-17 1989-12-19 Amdahl Corporation Apparatus and method for improving cache access throughput in pipelined processors
US4855947A (en) * 1987-05-27 1989-08-08 Amdahl Corporation Microprogrammable pipeline interlocks based on the validity of pipeline states
CA1302584C (en) * 1987-07-30 1992-06-02 Alliant Computer Systems Corporation Parallel processing computer in which memory access priorities are varied
US5222223A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Method and apparatus for ordering and queueing multiple memory requests
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5283873A (en) * 1990-06-29 1994-02-01 Digital Equipment Corporation Next line prediction apparatus for a pipelined computed system
JP3102594B2 (ja) * 1991-02-19 2000-10-23 松下電器産業株式会社 キャッシュメモリ装置
JP3304444B2 (ja) * 1992-11-30 2002-07-22 富士通株式会社 ベクトル処理装置
US6256068B1 (en) 1996-05-08 2001-07-03 Matsushita Electric Industrial Co., Ltd. Image data format conversion apparatus
US6055607A (en) * 1996-12-23 2000-04-25 Unisys Corporation Interface queue with bypassing capability for main storage unit
US10534712B1 (en) * 2016-08-29 2020-01-14 Infinidat Ltd. Service level agreement based management of a pre-cache module

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810114A (en) * 1971-12-29 1974-05-07 Tokyo Shibaura Electric Co Data processing system
IT971304B (it) * 1972-11-29 1974-04-30 Honeywell Inf Systems Sistema di accesso a priorita variabile dinamicamente
US4020468A (en) * 1974-12-10 1977-04-26 Westinghouse Electric Corporation Compressed information system
US4009470A (en) * 1975-02-18 1977-02-22 Sperry Rand Corporation Pre-emptive, rotational priority system
US4121285A (en) * 1977-04-01 1978-10-17 Ultronic Systems Corporation Automatic alternator for priority circuit
US4399503A (en) * 1978-06-30 1983-08-16 Bunker Ramo Corporation Dynamic disk buffer control unit
US4231091A (en) * 1978-11-27 1980-10-28 General Motors Corporation Engine control system
US4394728A (en) * 1980-06-26 1983-07-19 Gte Automatic Electric Labs Inc. Allocation controller providing for access of multiple common resources by a duplex plurality of central processing units
JPS5730168A (en) * 1980-07-29 1982-02-18 Nec Corp Cash memory access system
US4394727A (en) * 1981-05-04 1983-07-19 International Business Machines Corporation Multi-processor task dispatching apparatus
US4477872A (en) * 1982-01-15 1984-10-16 International Business Machines Corporation Decode history table for conditional branch instructions

Also Published As

Publication number Publication date
EP0265108B1 (de) 1994-02-09
US4722046A (en) 1988-01-26
AU7983987A (en) 1988-04-21
AU597117B2 (en) 1990-05-24
EP0265108A3 (en) 1990-01-31
JPS63191253A (ja) 1988-08-08
CA1286782C (en) 1991-07-23
EP0265108A2 (de) 1988-04-27

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Legal Events

Date Code Title Description
8332 No legal effect for de