DE3789929T2 - Verfahren und Gerät zur Fehlerkorrektur in einem aus parallelem Prozessor bestehenden Datenverarbeitungssystem. - Google Patents

Verfahren und Gerät zur Fehlerkorrektur in einem aus parallelem Prozessor bestehenden Datenverarbeitungssystem.

Info

Publication number
DE3789929T2
DE3789929T2 DE3789929T DE3789929T DE3789929T2 DE 3789929 T2 DE3789929 T2 DE 3789929T2 DE 3789929 T DE3789929 T DE 3789929T DE 3789929 T DE3789929 T DE 3789929T DE 3789929 T2 DE3789929 T2 DE 3789929T2
Authority
DE
Germany
Prior art keywords
data
parallel processor
read
error correction
error correcting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3789929T
Other languages
English (en)
Other versions
DE3789929D1 (de
Inventor
W Daniel Hillis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thinking Machines Corp
Original Assignee
Thinking Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thinking Machines Corp filed Critical Thinking Machines Corp
Application granted granted Critical
Publication of DE3789929D1 publication Critical patent/DE3789929D1/de
Publication of DE3789929T2 publication Critical patent/DE3789929T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
DE3789929T 1986-09-15 1987-09-15 Verfahren und Gerät zur Fehlerkorrektur in einem aus parallelem Prozessor bestehenden Datenverarbeitungssystem. Expired - Fee Related DE3789929T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/907,671 US4791641A (en) 1986-09-15 1986-09-15 Parallel processor error checking

Publications (2)

Publication Number Publication Date
DE3789929D1 DE3789929D1 (de) 1994-07-07
DE3789929T2 true DE3789929T2 (de) 1994-09-08

Family

ID=25424453

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3789929T Expired - Fee Related DE3789929T2 (de) 1986-09-15 1987-09-15 Verfahren und Gerät zur Fehlerkorrektur in einem aus parallelem Prozessor bestehenden Datenverarbeitungssystem.

Country Status (7)

Country Link
US (1) US4791641A (de)
EP (1) EP0261031B1 (de)
JP (1) JP2738687B2 (de)
AT (1) ATE106582T1 (de)
AU (1) AU7820987A (de)
CA (1) CA1292579C (de)
DE (1) DE3789929T2 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3706734C1 (de) * 1987-03-02 1988-03-17 Force Computers Gmbh Verfahren zur UEbertragung von Daten sowie Computer
US5170482A (en) * 1987-08-14 1992-12-08 Regents Of The University Of Minnesota Improved hypercube topology for multiprocessor computer systems
EP0343742B1 (de) * 1988-05-27 1995-08-09 Philips Electronics Uk Limited Dekoder für Hamming kodierte Daten
US5283791A (en) * 1988-08-02 1994-02-01 Cray Research Systems, Inc. Error recovery method and apparatus for high performance disk drives
US5218689A (en) * 1988-08-16 1993-06-08 Cray Research, Inc. Single disk emulation interface for an array of asynchronously operating disk drives
US5146461A (en) * 1989-11-13 1992-09-08 Solbourne Computer, Inc. Memory error correction system distributed on a high performance multiprocessor bus and method therefor
US5170370A (en) * 1989-11-17 1992-12-08 Cray Research, Inc. Vector bit-matrix multiply functional unit
US5280474A (en) * 1990-01-05 1994-01-18 Maspar Computer Corporation Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
AU645785B2 (en) * 1990-01-05 1994-01-27 Maspar Computer Corporation Parallel processor memory system
US5442797A (en) * 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
WO1993015460A2 (en) * 1992-01-24 1993-08-05 Digital Equipment Corporation Databus parity and high speed normalization circuit for a massively parallel processing system
EP0800133A1 (de) * 1992-01-24 1997-10-08 Digital Equipment Corporation Paritäts- und Hochgeschwindigkeitsnormierungskreis für ein massivparalleles Verarbeitungssystem
US5524212A (en) * 1992-04-27 1996-06-04 University Of Washington Multiprocessor system with write generate method for updating cache
GB2268817B (en) * 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
US5432801A (en) * 1993-07-23 1995-07-11 Commodore Electronics Limited Method and apparatus for performing multiple simultaneous error detection on data having unknown format
US5771247A (en) * 1994-10-03 1998-06-23 International Business Machines Corporation Low latency error reporting for high performance bus
US6836838B1 (en) 1998-06-29 2004-12-28 Cisco Technology, Inc. Architecture for a processor complex of an arrayed pipelined processing engine
US6119215A (en) 1998-06-29 2000-09-12 Cisco Technology, Inc. Synchronization and control system for an arrayed processing engine
US6513108B1 (en) 1998-06-29 2003-01-28 Cisco Technology, Inc. Programmable processing engine for efficiently processing transient data
US6101599A (en) * 1998-06-29 2000-08-08 Cisco Technology, Inc. System for context switching between processing elements in a pipeline of processing elements
US6195739B1 (en) 1998-06-29 2001-02-27 Cisco Technology, Inc. Method and apparatus for passing data among processor complex stages of a pipelined processing engine
US6356548B1 (en) 1998-06-29 2002-03-12 Cisco Technology, Inc. Pooled receive and transmit queues to access a shared bus in a multi-port switch asic
US6728839B1 (en) 1998-10-28 2004-04-27 Cisco Technology, Inc. Attribute based memory pre-fetching technique
US6175941B1 (en) 1998-12-08 2001-01-16 Lsi Logic Corporation Error correction apparatus and associated method utilizing parellel processing
US6385747B1 (en) 1998-12-14 2002-05-07 Cisco Technology, Inc. Testing of replicated components of electronic device
US6173386B1 (en) 1998-12-14 2001-01-09 Cisco Technology, Inc. Parallel processor with debug capability
US6920562B1 (en) 1998-12-18 2005-07-19 Cisco Technology, Inc. Tightly coupled software protocol decode with hardware data encryption
US6681341B1 (en) 1999-11-03 2004-01-20 Cisco Technology, Inc. Processor isolation method for integrated multi-processor systems
US6529983B1 (en) 1999-11-03 2003-03-04 Cisco Technology, Inc. Group and virtual locking mechanism for inter processor synchronization
US6892237B1 (en) 2000-03-28 2005-05-10 Cisco Technology, Inc. Method and apparatus for high-speed parsing of network messages
US6505269B1 (en) 2000-05-16 2003-01-07 Cisco Technology, Inc. Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
US7447872B2 (en) * 2002-05-30 2008-11-04 Cisco Technology, Inc. Inter-chip processor control plane communication
AU2011235311B2 (en) 2010-04-02 2013-09-26 3M Innovative Properties Company Filter systems including patterned optical analyte sensors and optical readers
JP2020198044A (ja) * 2019-06-05 2020-12-10 富士通株式会社 並列処理装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3660646A (en) * 1970-09-22 1972-05-02 Ibm Checking by pseudoduplication
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4215395A (en) * 1978-08-24 1980-07-29 Texas Instruments Incorporated Dual microprocessor intelligent programmable process control system
US4310879A (en) * 1979-03-08 1982-01-12 Pandeya Arun K Parallel processor having central processor memory extension
US4240156A (en) * 1979-03-29 1980-12-16 Doland George D Concatenated error correcting system
US4255808A (en) * 1979-04-19 1981-03-10 Sperry Corporation Hard or soft cell failure differentiator
US4295218A (en) * 1979-06-25 1981-10-13 Regents Of The University Of California Error-correcting coding system
US4314350A (en) * 1979-12-31 1982-02-02 Bell Telephone Laboratories, Incorporated Self-checking arithmetic unit
US4371930A (en) * 1980-06-03 1983-02-01 Burroughs Corporation Apparatus for detecting, correcting and logging single bit memory read errors
US4345328A (en) * 1980-06-30 1982-08-17 Sperry Corporation ECC Check bit generation using through checking parity bits
JPS57100698A (en) * 1980-12-15 1982-06-22 Fujitsu Ltd Error correction system
US4414669A (en) * 1981-07-23 1983-11-08 General Electric Company Self-testing pipeline processors
US4473902A (en) * 1982-04-22 1984-09-25 Sperrt Corporation Error correcting code processing system
JPS5985153A (ja) * 1982-11-08 1984-05-17 Hitachi Ltd 冗長化制御装置
US4604750A (en) * 1983-11-07 1986-08-05 Digital Equipment Corporation Pipeline error correction
JPH0654505B2 (ja) * 1983-12-23 1994-07-20 株式会社日立製作所 並列型演算処理装置

Also Published As

Publication number Publication date
EP0261031B1 (de) 1994-06-01
EP0261031A2 (de) 1988-03-23
US4791641A (en) 1988-12-13
CA1292579C (en) 1991-11-26
JP2738687B2 (ja) 1998-04-08
ATE106582T1 (de) 1994-06-15
AU7820987A (en) 1988-03-17
JPS6394353A (ja) 1988-04-25
DE3789929D1 (de) 1994-07-07
EP0261031A3 (en) 1989-11-02

Similar Documents

Publication Publication Date Title
DE3789929D1 (de) Verfahren und Gerät zur Fehlerkorrektur in einem aus parallelem Prozessor bestehenden Datenverarbeitungssystem.
NO954028L (no) Fremgangsmåte for å laste inn i et beskyttet lagerområde i en informasjons-behandlingsanordning, samt anordning for dette formål
DE69131272T2 (de) Paralleles Assoziativprozessor-System
DE3481236D1 (de) Vorrichtung zum steuern des zugangs zu einem speicher.
ES514648A0 (es) Un subsistema de memoria capaz de financiar en diversos modos, para un sistema de tratamiento de datos, o incluido en elmismo.
SE8302511L (sv) Anordning for att skydda mot obehorig lesning av programord som er lagrade i ett minne
DE69019822D1 (de) Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung.
DE3380752D1 (en) Apparatus for error correction
DE68927434D1 (de) Lese-Ändern-Schreiben Funktion
KR840007190A (ko) 버퍼기억장치의 단일비트 에러처리 시스템
DK264287A (da) Pagineret lager til en databehandlingsenhed
DE3772406D1 (de) Dekodiergeraet.
JPS5730838A (en) Layout processing system
SE8104981L (sv) Metod och anordning for adressering av ett minne
DE69224566D1 (de) Integrierte Speicherschaltung mit redundanten Zeilen
DE3276503D1 (en) Data processing system allowing use of the same erasable and programmable memory for both reading and writing instructions and data
IT1177492B (it) Sistema di elaboratore con sicurezza di memoria migliorata
EP0375892A3 (de) Datenverarbeitungsanordnung
JPS57174750A (en) Data processor
JPS57152600A (en) Duplicating system of memory device
JPS5424612A (en) Error detecting system of data memory device
JPS5769583A (en) Non_volatile semiconductor memory
JPS576954A (en) Multiprocessor system
JPS5387137A (en) Data processing system
JPS57763A (en) External memory device

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee