DE69224566D1 - Integrierte Speicherschaltung mit redundanten Zeilen - Google Patents

Integrierte Speicherschaltung mit redundanten Zeilen

Info

Publication number
DE69224566D1
DE69224566D1 DE69224566T DE69224566T DE69224566D1 DE 69224566 D1 DE69224566 D1 DE 69224566D1 DE 69224566 T DE69224566 T DE 69224566T DE 69224566 T DE69224566 T DE 69224566T DE 69224566 D1 DE69224566 D1 DE 69224566D1
Authority
DE
Germany
Prior art keywords
array
redundant
data
rows
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224566T
Other languages
English (en)
Other versions
DE69224566T2 (de
Inventor
Bahador Rastegar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69224566D1 publication Critical patent/DE69224566D1/de
Publication of DE69224566T2 publication Critical patent/DE69224566T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/818—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for dual-port memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
DE69224566T 1991-07-17 1992-07-16 Integrierte Speicherschaltung mit redundanten Zeilen Expired - Fee Related DE69224566T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/731,487 US5297094A (en) 1991-07-17 1991-07-17 Integrated circuit memory device with redundant rows

Publications (2)

Publication Number Publication Date
DE69224566D1 true DE69224566D1 (de) 1998-04-09
DE69224566T2 DE69224566T2 (de) 1998-07-23

Family

ID=24939710

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224566T Expired - Fee Related DE69224566T2 (de) 1991-07-17 1992-07-16 Integrierte Speicherschaltung mit redundanten Zeilen

Country Status (4)

Country Link
US (1) US5297094A (de)
EP (1) EP0523996B1 (de)
JP (1) JPH05210999A (de)
DE (1) DE69224566T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3181001B2 (ja) * 1993-06-01 2001-07-03 インターナショナル・ビジネス・マシーンズ・コーポレ−ション キャッシュ・メモリ・システム並びにキャッシュ・メモリ・アクセス方法及びシステム
US5815512A (en) * 1994-05-26 1998-09-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory testing device
JP2850953B2 (ja) * 1996-07-30 1999-01-27 日本電気株式会社 半導体装置
US6034879A (en) * 1998-02-19 2000-03-07 University Of Pittsburgh Twisted line techniques for multi-gigabit dynamic random access memories
US6072735A (en) * 1998-06-22 2000-06-06 Lucent Technologies, Inc. Built-in redundancy architecture for computer memories
US20030191885A1 (en) * 2002-04-09 2003-10-09 Chandra Thimmanagari On-chip cache redundancy technique
US6990011B2 (en) * 2003-05-09 2006-01-24 Stmicroelectronics, Inc. Memory circuit and method for corrupting stored data
US7224600B2 (en) * 2004-01-08 2007-05-29 Stmicroelectronics, Inc. Tamper memory cell
US7962880B2 (en) * 2008-02-22 2011-06-14 International Business Machines Corporation Wire structures minimizing coupling effects between wires in a bus
JP2011181131A (ja) 2010-02-26 2011-09-15 Toshiba Corp 半導体記憶装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3942164A (en) * 1975-01-30 1976-03-02 Semi, Inc. Sense line coupling reduction system
JPS59121699A (ja) * 1982-12-28 1984-07-13 Toshiba Corp 冗長性回路変更装置
US4870619A (en) * 1986-10-14 1989-09-26 Monolithic Systems Corp. Memory chip array with inverting and non-inverting address drivers
JPH02302986A (ja) * 1989-05-16 1990-12-14 Mitsubishi Electric Corp ダイナミック型半導体記憶装置
KR930001737B1 (ko) * 1989-12-29 1993-03-12 삼성전자 주식회사 반도체 메모리 어레이의 워드라인 배열방법
US5339322A (en) * 1991-03-29 1994-08-16 Sgs-Thomson Microelectronics, Inc. Cache tag parity detect circuit

Also Published As

Publication number Publication date
US5297094A (en) 1994-03-22
EP0523996A1 (de) 1993-01-20
JPH05210999A (ja) 1993-08-20
DE69224566T2 (de) 1998-07-23
EP0523996B1 (de) 1998-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee