JPS57174750A - Data processor - Google Patents

Data processor

Info

Publication number
JPS57174750A
JPS57174750A JP56058539A JP5853981A JPS57174750A JP S57174750 A JPS57174750 A JP S57174750A JP 56058539 A JP56058539 A JP 56058539A JP 5853981 A JP5853981 A JP 5853981A JP S57174750 A JPS57174750 A JP S57174750A
Authority
JP
Japan
Prior art keywords
sequence
register
address
memory element
range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56058539A
Other languages
Japanese (ja)
Inventor
Seiichiro Yamamoto
Hitotsugu Ukon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56058539A priority Critical patent/JPS57174750A/en
Publication of JPS57174750A publication Critical patent/JPS57174750A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To eliminate the pine neck of an LSi or a card, by setting the mounting range of the memory element and at the same time carrying a test for the propriety of the set range. CONSTITUTION:The minimum mounting capacity -1 of a memory element A is set tentatively to a register 5 with a sequence 2. The process proceeds to a sequence 4, and the address value is added and set to the register 51. Then the test data to be given to a memory is written in and read out of the address with sequences 6, 7 and 8. The correct reading/writing is possible if the address comprises the element A, and a sequence 9 gives YES through its decision. Thus the process returns to the sequence 3. In case the address comprises a memory element B, the decision shows NO. Thus the contents of the register 51 are made to minus 32 and 768 to set the mounting range of the element A.
JP56058539A 1981-04-20 1981-04-20 Data processor Pending JPS57174750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56058539A JPS57174750A (en) 1981-04-20 1981-04-20 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56058539A JPS57174750A (en) 1981-04-20 1981-04-20 Data processor

Publications (1)

Publication Number Publication Date
JPS57174750A true JPS57174750A (en) 1982-10-27

Family

ID=13087239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56058539A Pending JPS57174750A (en) 1981-04-20 1981-04-20 Data processor

Country Status (1)

Country Link
JP (1) JPS57174750A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62273691A (en) * 1986-05-22 1987-11-27 Canon Inc Electronic apparatus
JPS6418856A (en) * 1987-07-14 1989-01-23 Fujitsu Ltd Recognizing system for memory capacity
EP0335318A2 (en) * 1988-03-30 1989-10-04 Kabushiki Kaisha Toshiba Input and output control system
JPH0264752A (en) * 1988-08-30 1990-03-05 Fujitsu General Ltd Method for identifying memory expansion card in teletext receiver

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62273691A (en) * 1986-05-22 1987-11-27 Canon Inc Electronic apparatus
JPS6418856A (en) * 1987-07-14 1989-01-23 Fujitsu Ltd Recognizing system for memory capacity
EP0335318A2 (en) * 1988-03-30 1989-10-04 Kabushiki Kaisha Toshiba Input and output control system
JPH0264752A (en) * 1988-08-30 1990-03-05 Fujitsu General Ltd Method for identifying memory expansion card in teletext receiver

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