DE3784902D1 - Verfahren zur herstellung von verbindungslinien und von kreuzungspunkten verschiedener metallisierungsebenen auf einer integrierten schaltung. - Google Patents

Verfahren zur herstellung von verbindungslinien und von kreuzungspunkten verschiedener metallisierungsebenen auf einer integrierten schaltung.

Info

Publication number
DE3784902D1
DE3784902D1 DE8787202546T DE3784902T DE3784902D1 DE 3784902 D1 DE3784902 D1 DE 3784902D1 DE 8787202546 T DE8787202546 T DE 8787202546T DE 3784902 T DE3784902 T DE 3784902T DE 3784902 D1 DE3784902 D1 DE 3784902D1
Authority
DE
Germany
Prior art keywords
cross
integrated circuit
connection lines
point points
producing connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787202546T
Other languages
English (en)
Other versions
DE3784902T2 (de
Inventor
Patrick Societe Civi Rabinzohn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE3784902D1 publication Critical patent/DE3784902D1/de
Application granted granted Critical
Publication of DE3784902T2 publication Critical patent/DE3784902T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8787202546T 1986-12-23 1987-12-16 Verfahren zur herstellung von verbindungslinien und von kreuzungspunkten verschiedener metallisierungsebenen auf einer integrierten schaltung. Expired - Fee Related DE3784902T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8618048A FR2608839B1 (fr) 1986-12-23 1986-12-23 Procede de realisation d'interconnexions et de croisements entre niveaux de metallisation d'un circuit integre

Publications (2)

Publication Number Publication Date
DE3784902D1 true DE3784902D1 (de) 1993-04-22
DE3784902T2 DE3784902T2 (de) 1993-09-09

Family

ID=9342210

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787202546T Expired - Fee Related DE3784902T2 (de) 1986-12-23 1987-12-16 Verfahren zur herstellung von verbindungslinien und von kreuzungspunkten verschiedener metallisierungsebenen auf einer integrierten schaltung.

Country Status (6)

Country Link
US (1) US4803177A (de)
EP (1) EP0275595B1 (de)
JP (1) JP2730724B2 (de)
KR (1) KR880008419A (de)
DE (1) DE3784902T2 (de)
FR (1) FR2608839B1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303488B1 (en) 1997-02-12 2001-10-16 Micron Technology, Inc. Semiconductor processing methods of forming openings to devices and substrates, exposing material from which photoresist cannot be substantially selectively removed
US6060393A (en) * 1997-12-18 2000-05-09 Advanced Micro Devices, Inc. Deposition control of stop layer and dielectric layer for use in the formation of local interconnects
US5946592A (en) * 1998-03-19 1999-08-31 Winbond Electronics, Corp. Combined in-situ high density plasma enhanced chemical vapor deposition (HDPCVD) and chemical mechanical polishing (CMP) process to form an intermetal dielectric layer with a stopper layer embedded therein
US6495468B2 (en) 1998-12-22 2002-12-17 Micron Technology, Inc. Laser ablative removal of photoresist
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0057738B1 (de) * 1981-02-07 1986-10-15 Ibm Deutschland Gmbh Verfahren zum Herstellen und Füllen von Löchern in einer auf einem Substrat aufliegenden Schicht
JPS57170551A (en) * 1981-04-14 1982-10-20 Fujitsu Ltd Manufacture of semiconductor device
JPS58142546A (ja) * 1982-02-19 1983-08-24 Hitachi Denshi Ltd 多層配線の形成方法
FR2525389A1 (fr) * 1982-04-14 1983-10-21 Commissariat Energie Atomique Procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
FR2537779B1 (fr) * 1982-12-10 1986-03-14 Commissariat Energie Atomique Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre
JPS59181017A (ja) * 1983-03-30 1984-10-15 Fujitsu Ltd 半導体装置の製造方法
US4515652A (en) * 1984-03-20 1985-05-07 Harris Corporation Plasma sculpturing with a non-planar sacrificial layer
US4541893A (en) * 1984-05-15 1985-09-17 Advanced Micro Devices, Inc. Process for fabricating pedestal interconnections between conductive layers in an integrated circuit
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
US4568410A (en) * 1984-12-20 1986-02-04 Motorola, Inc. Selective plasma etching of silicon nitride in the presence of silicon oxide
JPS61164242A (ja) * 1985-01-17 1986-07-24 Seiko Epson Corp 半導体装置の製造方法
JPS61237450A (ja) * 1985-04-12 1986-10-22 Sharp Corp 半導体装置の製造方法
US4689113A (en) * 1986-03-21 1987-08-25 International Business Machines Corporation Process for forming planar chip-level wiring

Also Published As

Publication number Publication date
DE3784902T2 (de) 1993-09-09
FR2608839B1 (fr) 1989-04-21
FR2608839A1 (fr) 1988-06-24
KR880008419A (ko) 1988-08-31
JP2730724B2 (ja) 1998-03-25
US4803177A (en) 1989-02-07
EP0275595B1 (de) 1993-03-17
EP0275595A1 (de) 1988-07-27
JPS63168035A (ja) 1988-07-12

Similar Documents

Publication Publication Date Title
DE3784751T2 (de) Verfahren zur herstellung von verbindungsloechern auf integrierten schaltungen.
DE3686125D1 (de) Verfahren zur herstellung einer integrierten schaltung.
DE3673359D1 (de) Verfahren zur herstellung von gedruckten schaltungsplatten.
DE3782972T2 (de) Ic-karte und verfahren zur herstellung derselben.
DE3586666T2 (de) Karte mit ic-baustein und verfahren zur herstellung derselben.
DE3882412T2 (de) Verfahren zur Herstellung einer elektronischen Vorrichtung.
DE3785487D1 (de) Verfahren zur herstellung von traegern fuer gedruckte schaltungen.
DE3750418D1 (de) Zusammensetzungen und Verfahren zur Herstellung von wasserdispergierbaren Polymeren.
DE3769484D1 (de) Verfahren zur herstellung von gedruckten leiterplatten.
DE3871175D1 (de) Verfahren zur herstellung von perovskit und abo3-typ-oxyden.
DE3870633D1 (de) Verfahren zur herstellung von butyrolactonen und von butandiolen.
DE3580025D1 (de) Halbleiter auf isolator-(soi)-anordnungen und verfahren zur herstellung von soi integrierten schaltungen.
DE68928951D1 (de) Verfahren zur Herstellung einer integrierten Schaltung mit Bipolartransistoren
DE3767155D1 (de) Biegsame halbleiterplatte und verfahren zur herstellung.
DE3762855D1 (de) Verfahren zur herstellung von hydroxyalkylaminen und hydroxyalkylpiperazinen.
DE3878090D1 (de) Verfahren zur herstellung von supraleitenden schaltungen.
DE3771234D1 (de) Verfahren zur herstellung von ebenen und schalenfoermig gekruemmten bauteilen.
DE68919589D1 (de) Träger einer hoch integrierten Schaltung und Verfahren zur seiner Herstellung.
DE3887989T2 (de) Verfahren zur herstellung von gedruckten schaltungen mit durchgehenden löchern für metallisierung.
DE3684922D1 (de) Verfahren zur herstellung von 2-phenylbenzotriazolen und 2-phenylbenzotriazol-n-oxyden.
DE68923730D1 (de) Verfahren zur Herstellung einer bipolaren integrierten Schaltung.
DE3784902D1 (de) Verfahren zur herstellung von verbindungslinien und von kreuzungspunkten verschiedener metallisierungsebenen auf einer integrierten schaltung.
DE3771577D1 (de) Verfahren zur herstellung von diadenosintetraphosphat und derivaten davon.
DE3777556D1 (de) Verfahren zur herstellung von in elektronischen teilen verwendeter keramik.
DE3584332D1 (de) Verfahren zur herstellung von bohnenbruch und bohnenmilch.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee