DE3782735D1 - Ttl-kompatible cmos-eingangsschaltung. - Google Patents

Ttl-kompatible cmos-eingangsschaltung.

Info

Publication number
DE3782735D1
DE3782735D1 DE8888900310T DE3782735T DE3782735D1 DE 3782735 D1 DE3782735 D1 DE 3782735D1 DE 8888900310 T DE8888900310 T DE 8888900310T DE 3782735 T DE3782735 T DE 3782735T DE 3782735 D1 DE3782735 D1 DE 3782735D1
Authority
DE
Germany
Prior art keywords
input switching
ttl compatible
compatible cmos
cmos input
current mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888900310T
Other languages
English (en)
Other versions
DE3782735T2 (de
Inventor
C Dunn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE3782735D1 publication Critical patent/DE3782735D1/de
Application granted granted Critical
Publication of DE3782735T2 publication Critical patent/DE3782735T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE8888900310T 1987-01-02 1987-11-30 Ttl-kompatible cmos-eingangsschaltung. Expired - Fee Related DE3782735T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/000,192 US4717845A (en) 1987-01-02 1987-01-02 TTL compatible CMOS input circuit
PCT/US1987/003166 WO1988005228A1 (en) 1987-01-02 1987-11-30 Ttl compatible cmos input circuit

Publications (2)

Publication Number Publication Date
DE3782735D1 true DE3782735D1 (de) 1992-12-24
DE3782735T2 DE3782735T2 (de) 1993-04-01

Family

ID=21690333

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888900310T Expired - Fee Related DE3782735T2 (de) 1987-01-02 1987-11-30 Ttl-kompatible cmos-eingangsschaltung.

Country Status (6)

Country Link
US (1) US4717845A (de)
EP (1) EP0296193B1 (de)
JP (1) JP2917222B2 (de)
AT (1) ATE82656T1 (de)
DE (1) DE3782735T2 (de)
WO (1) WO1988005228A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4841175A (en) * 1987-01-23 1989-06-20 Siemens Aktiengesellschaft ECL-compatible input/output circuits in CMOS technology
US4825099A (en) * 1987-12-04 1989-04-25 Ford Microelectronics Feedback-controlled current output driver having reduced current surge
US4845388A (en) * 1988-01-20 1989-07-04 Martin Marietta Corporation TTL-CMOS input buffer
GB2217937A (en) * 1988-04-29 1989-11-01 Philips Electronic Associated Current divider circuit
US5019729A (en) * 1988-07-27 1991-05-28 Kabushiki Kaisha Toshiba TTL to CMOS buffer circuit
US4916337A (en) * 1989-03-07 1990-04-10 Integrated Device Technology, Inc. TTL to CMOS logic level translator
JP2724872B2 (ja) * 1989-04-12 1998-03-09 三菱電機株式会社 半導体集積回路用入力回路
US5243239A (en) * 1991-01-22 1993-09-07 Information Storage Devices, Inc. Integrated MOSFET resistance and oscillator frequency control and trim methods and apparatus
JP3168425B2 (ja) * 1991-01-22 2001-05-21 インフォメーション・ストレジ・デバイシーズ・インコーポレーテッド 集積ｍｏｓｆｅｔ抵抗及び発振器周波数の制御及びトリム方法とその装置
JP3436971B2 (ja) * 1994-06-03 2003-08-18 三菱電機株式会社 電圧制御型電流源およびそれを用いたバイアス発生回路
GB2335556B (en) 1998-03-18 2002-10-30 Ericsson Telefon Ab L M Switch circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4438352A (en) * 1980-06-02 1984-03-20 Xerox Corporation TTL Compatible CMOS input buffer
US4380710A (en) * 1981-02-05 1983-04-19 Harris Corporation TTL to CMOS Interface circuit
US4437025A (en) * 1981-07-29 1984-03-13 Intel Corporation MOS Buffer for receiving TTL level signals
US4485317A (en) * 1981-10-02 1984-11-27 Fairchild Camera & Instrument Corp. Dynamic TTL input comparator for CMOS devices
US4475050A (en) * 1981-12-21 1984-10-02 Motorola, Inc. TTL To CMOS input buffer
US4471242A (en) * 1981-12-21 1984-09-11 Motorola, Inc. TTL to CMOS Input buffer
US4490633A (en) * 1981-12-28 1984-12-25 Motorola, Inc. TTL to CMOS input buffer
DE3300869A1 (de) * 1982-01-26 1983-08-04 Deutsche Itt Industries Gmbh, 7800 Freiburg Logischer cmos-schaltkreis
US4469959A (en) * 1982-03-15 1984-09-04 Motorola, Inc. Input buffer
US4529948A (en) * 1983-02-22 1985-07-16 Intersil, Inc. Class AB amplifier
DE3323446A1 (de) * 1983-06-29 1985-01-10 Siemens AG, 1000 Berlin und 8000 München Eingangssignalpegelwandler fuer eine mos-digitalschaltung
US4555642A (en) * 1983-09-22 1985-11-26 Standard Microsystems Corporation Low power CMOS input buffer circuit
US4584491A (en) * 1984-01-12 1986-04-22 Motorola, Inc. TTL to CMOS input buffer circuit for minimizing power consumption

Also Published As

Publication number Publication date
JPH01502468A (ja) 1989-08-24
EP0296193A4 (de) 1989-12-28
WO1988005228A1 (en) 1988-07-14
DE3782735T2 (de) 1993-04-01
EP0296193A1 (de) 1988-12-28
EP0296193B1 (de) 1992-11-19
ATE82656T1 (de) 1992-12-15
US4717845A (en) 1988-01-05
JP2917222B2 (ja) 1999-07-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee