DE3686901D1 - Auf hohem systemniveau selbstpruefendes intelligentes e/a-steuergeraet. - Google Patents

Auf hohem systemniveau selbstpruefendes intelligentes e/a-steuergeraet.

Info

Publication number
DE3686901D1
DE3686901D1 DE8686303566T DE3686901T DE3686901D1 DE 3686901 D1 DE3686901 D1 DE 3686901D1 DE 8686303566 T DE8686303566 T DE 8686303566T DE 3686901 T DE3686901 T DE 3686901T DE 3686901 D1 DE3686901 D1 DE 3686901D1
Authority
DE
Germany
Prior art keywords
true
data
complement
errors
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686303566T
Other languages
English (en)
Other versions
DE3686901T2 (de
Inventor
Srikumar R Chandran
Mark S Walker
Edward J Rhodes
Albert S Lui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Application granted granted Critical
Publication of DE3686901D1 publication Critical patent/DE3686901D1/de
Publication of DE3686901T2 publication Critical patent/DE3686901T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1654—Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Alarm Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Debugging And Monitoring (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Control Of Throttle Valves Provided In The Intake System Or In The Exhaust System (AREA)
  • Control Of Transmission Device (AREA)
  • Testing And Monitoring For Control Systems (AREA)
DE8686303566T 1985-05-10 1986-05-09 Auf hohem systemniveau selbstpruefendes intelligentes e/a-steuergeraet. Expired - Lifetime DE3686901T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US73367985A 1985-05-10 1985-05-10

Publications (2)

Publication Number Publication Date
DE3686901D1 true DE3686901D1 (de) 1992-11-12
DE3686901T2 DE3686901T2 (de) 1993-02-18

Family

ID=24948680

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686303566T Expired - Lifetime DE3686901T2 (de) 1985-05-10 1986-05-09 Auf hohem systemniveau selbstpruefendes intelligentes e/a-steuergeraet.

Country Status (8)

Country Link
US (1) US4785453A (de)
EP (1) EP0201356B1 (de)
JP (1) JPH0792765B2 (de)
AT (1) ATE81412T1 (de)
AU (1) AU568977B2 (de)
CA (1) CA1259415A (de)
DE (1) DE3686901T2 (de)
NO (1) NO174406C (de)

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US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
US5203004A (en) * 1990-01-08 1993-04-13 Tandem Computers Incorporated Multi-board system having electronic keying and preventing power to improperly connected plug-in board with improperly configured diode connections
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US6247144B1 (en) * 1991-01-31 2001-06-12 Compaq Computer Corporation Method and apparatus for comparing real time operation of object code compatible processors
US5392302A (en) * 1991-03-13 1995-02-21 Quantum Corp. Address error detection technique for increasing the reliability of a storage subsystem
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US5758058A (en) * 1993-03-31 1998-05-26 Intel Corporation Apparatus and method for initializing a master/checker fault detecting microprocessor
JP3264465B2 (ja) 1993-06-30 2002-03-11 株式会社日立製作所 記憶システム
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US6175883B1 (en) * 1995-11-21 2001-01-16 Quantum Corporation System for increasing data transfer rate using sychronous DMA transfer protocol by reducing a timing delay at both sending and receiving devices
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US5978938A (en) * 1996-11-19 1999-11-02 International Business Machines Corporation Fault isolation feature for an I/O or system bus
US5857069A (en) * 1996-12-30 1999-01-05 Lucent Technologies Inc. Technique for recovering defective memory
US5908471A (en) * 1997-01-31 1999-06-01 Sun Microsystems, Inc Diagnostic arrangement for digital computer system
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US6058449A (en) * 1997-07-31 2000-05-02 Motorola, Inc. Fault tolerant serial arbitration system
US6256753B1 (en) * 1998-06-30 2001-07-03 Sun Microsystems, Inc. Bus error handling in a computer system
DE19850672C2 (de) * 1998-11-03 2003-07-31 St Microelectronics Gmbh Leitungsfehlerprüfschaltung für ein elektrisches Datenübertragungssystem
US7012927B2 (en) 2001-02-06 2006-03-14 Honeywell International Inc. High level message priority assignment by a plurality of message-sending nodes sharing a signal bus
US7333504B2 (en) * 2001-03-08 2008-02-19 Honeywell International Inc. Simultaneous serial transmission of messages with data field arbitration
US20040073721A1 (en) * 2002-10-10 2004-04-15 Koninklijke Philips Electronics N.V. DMA Controller for USB and like applications
US7237144B2 (en) 2004-04-06 2007-06-26 Hewlett-Packard Development Company, L.P. Off-chip lockstep checking
US7290169B2 (en) 2004-04-06 2007-10-30 Hewlett-Packard Development Company, L.P. Core-level processor lockstepping
US7296181B2 (en) 2004-04-06 2007-11-13 Hewlett-Packard Development Company, L.P. Lockstep error signaling
US7546441B1 (en) 2004-08-06 2009-06-09 Xilinx, Inc. Coprocessor interface controller
US7590822B1 (en) 2004-08-06 2009-09-15 Xilinx, Inc. Tracking an instruction through a processor pipeline
US7590823B1 (en) 2004-08-06 2009-09-15 Xilinx, Inc. Method and system for handling an instruction not supported in a coprocessor formed using configurable logic
US7346759B1 (en) 2004-08-06 2008-03-18 Xilinx, Inc. Decoder interface
US7243212B1 (en) * 2004-08-06 2007-07-10 Xilinx, Inc. Processor-controller interface for non-lock step operation
DE102005037222A1 (de) * 2004-10-25 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Auswertung eines Signals eines Rechnersystems mit wenigstens zwei Ausführungseinheiten
JP2008518298A (ja) * 2004-10-25 2008-05-29 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング 複数のコンポーネントを有する計算機システムで信号を生成するための方法および装置
DE102004058288A1 (de) * 2004-12-02 2006-06-08 Robert Bosch Gmbh Vorrichtung und Verfahren zur Behebung von Fehlern bei einem Prozessor mit zwei Ausführungseinheiten
EP1712996A1 (de) * 2005-04-15 2006-10-18 STMicroelectronics S.r.l. Verfahren und System zur Konfiguration von Registern in Mikrocontrollern, entsprechender Mikrocontroller und Computerprogrammprodukt
US7769932B2 (en) * 2005-09-09 2010-08-03 Honeywell International, Inc. Bitwise arbitration on a serial bus using arbitrarily selected nodes for bit synchronization
DE102006002824B4 (de) 2006-01-19 2008-10-09 Phoenix Contact Gmbh & Co. Kg Verfahren und Vorrichtung zur Umwandlung mehrkanalig vorliegender Nachrichten in eine einkanalige sichere Nachricht
US7680144B2 (en) * 2006-09-12 2010-03-16 Honeywell International Inc. Device coupled between serial busses using bitwise arbitration
JP5308629B2 (ja) 2007-03-26 2013-10-09 ルネサスエレクトロニクス株式会社 マルチプロセッサシステム及びマルチプロセッサシステムにおけるアクセス保護方法
US8140629B2 (en) * 2008-09-30 2012-03-20 Pivot Solutions, Inc. System and method for processing instant messages
JP5404437B2 (ja) * 2010-01-13 2014-01-29 株式会社東芝 安全出力装置
RU2453079C2 (ru) * 2010-08-17 2012-06-10 Елена Геннадиевна Тимофеева Устройство для контроля и резервирования информационной системы
CN103901772B (zh) * 2014-04-23 2016-04-13 哈尔滨工业大学 双dsp冗余惯性平台控制器
US10078565B1 (en) * 2016-06-16 2018-09-18 Xilinx, Inc. Error recovery for redundant processing circuits
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US12099096B2 (en) 2022-02-07 2024-09-24 Hamilton Sundstrand Corporation Built in test (BIT) for transformer rectifier unit (TRU) backfeed interlock

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Also Published As

Publication number Publication date
ATE81412T1 (de) 1992-10-15
JPS6231441A (ja) 1987-02-10
NO174406B (no) 1994-01-17
DE3686901T2 (de) 1993-02-18
CA1259415A (en) 1989-09-12
NO861863L (no) 1986-11-11
EP0201356B1 (de) 1992-10-07
EP0201356A2 (de) 1986-11-12
AU568977B2 (en) 1988-01-14
NO174406C (no) 1994-04-27
US4785453A (en) 1988-11-15
EP0201356A3 (en) 1988-11-30
AU5720486A (en) 1986-11-13
JPH0792765B2 (ja) 1995-10-09

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