DE3685871D1 - Komplementaere halbleitereinrichtung mit einem substratspannungsgenerator. - Google Patents

Komplementaere halbleitereinrichtung mit einem substratspannungsgenerator.

Info

Publication number
DE3685871D1
DE3685871D1 DE8686306277T DE3685871T DE3685871D1 DE 3685871 D1 DE3685871 D1 DE 3685871D1 DE 8686306277 T DE8686306277 T DE 8686306277T DE 3685871 T DE3685871 T DE 3685871T DE 3685871 D1 DE3685871 D1 DE 3685871D1
Authority
DE
Germany
Prior art keywords
complemental
semiconductor device
voltage generator
substrate voltage
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686306277T
Other languages
English (en)
Other versions
DE3685871T2 (de
Inventor
Tomio Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3685871D1 publication Critical patent/DE3685871D1/de
Application granted granted Critical
Publication of DE3685871T2 publication Critical patent/DE3685871T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8686306277T 1985-08-14 1986-08-14 Komplementaere halbleitereinrichtung mit einem substratspannungsgenerator. Expired - Fee Related DE3685871T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60178958A JPS6238591A (ja) 1985-08-14 1985-08-14 相補型の半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE3685871D1 true DE3685871D1 (de) 1992-08-06
DE3685871T2 DE3685871T2 (de) 1992-12-17

Family

ID=16057632

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686306277T Expired - Fee Related DE3685871T2 (de) 1985-08-14 1986-08-14 Komplementaere halbleitereinrichtung mit einem substratspannungsgenerator.

Country Status (5)

Country Link
US (1) US4862415A (de)
EP (1) EP0222472B1 (de)
JP (1) JPS6238591A (de)
KR (1) KR900002621B1 (de)
DE (1) DE3685871T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666443B2 (ja) * 1988-07-07 1994-08-24 株式会社東芝 半導体メモリセルおよび半導体メモリ
US4965466A (en) * 1989-07-19 1990-10-23 Motorola, Inc. Substrate injection clamp
EP0441201B1 (de) * 1990-02-05 1996-05-15 Texas Instruments Incorporated Substratvorspannung Detektorschaltung
KR940005515B1 (ko) * 1990-02-26 1994-06-20 니뽄 덴끼 가부시끼가이샤 디코더 회로
JP3107556B2 (ja) * 1990-06-01 2000-11-13 株式会社東芝 ダイナミック型半導体記憶装置
US5341035A (en) * 1990-06-04 1994-08-23 Matsushita Electric Industrial Co., Ltd. Substrate potential generator
US5345422A (en) * 1990-07-31 1994-09-06 Texas Instruments Incorporated Power up detection circuit
EP0573009B1 (de) * 1992-06-02 1996-10-16 Kabushiki Kaisha Toshiba Halbleiterschaltung
JPH10502181A (ja) * 1994-06-20 1998-02-24 ネオマジック・コーポレイション メモリインタフェースのないグラフィックスコントローラ集積回路
KR0172333B1 (ko) * 1995-01-16 1999-03-30 김광호 반도체 메모리 장치의 전원 승압 회로
JPH08272467A (ja) * 1995-03-31 1996-10-18 Mitsubishi Electric Corp 基板電位発生回路
FR2735922B1 (fr) * 1995-06-21 1997-08-22 Sgs Thomson Microelectronics Circuit generateur de tension negative du type pompe de charge
JPH1079193A (ja) * 1996-07-11 1998-03-24 Toshiba Microelectron Corp 半導体装置
US5883544A (en) * 1996-12-03 1999-03-16 Stmicroelectronics, Inc. Integrated circuit actively biasing the threshold voltage of transistors and related methods
US6657241B1 (en) 1998-04-10 2003-12-02 Cypress Semiconductor Corp. ESD structure having an improved noise immunity in CMOS and BICMOS semiconductor devices
US6292391B1 (en) 2000-03-28 2001-09-18 Silicon Storage Technology, Inc. Isolation circuit and method for controlling discharge of high-voltage in a flash EEPROM
EP1965425A1 (de) * 2007-03-01 2008-09-03 Infineon Technologies Austria AG Integrierte Schaltungsanordnung mit Gegenspannungsschutz
US8013475B2 (en) 2007-03-15 2011-09-06 Infineon Technologies Ag Reverse voltage protected integrated circuit arrangement for multiple supply lines
JP6263833B2 (ja) * 2012-10-22 2018-01-24 株式会社ソシオネクスト 電子回路および半導体装置
FR3018944A1 (fr) * 2014-03-21 2015-09-25 St Microelectronics Rousset Dispositif de memoire associant un plan memoire du type sram et un plan-memoire du type non volatil, durci contre des basculements accidentels
US10204906B2 (en) * 2016-12-16 2019-02-12 Intel Corporation Memory with single-event latchup prevention circuitry

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951071B2 (ja) * 1976-02-09 1984-12-12 日本電気株式会社 メモリ保護回路
US4337524A (en) * 1980-02-07 1982-06-29 Mostek Corporation Backup power circuit for biasing bit lines of a static semiconductor memory
US4322675A (en) * 1980-11-03 1982-03-30 Fairchild Camera & Instrument Corp. Regulated MOS substrate bias voltage generator for a static random access memory
US4638464A (en) * 1983-11-14 1987-01-20 International Business Machines Corp. Charge pump system for non-volatile ram
US4631421A (en) * 1984-08-14 1986-12-23 Texas Instruments CMOS substrate bias generator
US4678941A (en) * 1985-04-25 1987-07-07 International Business Machines Corporation Boost word-line clock and decoder-driver circuits in semiconductor memories

Also Published As

Publication number Publication date
EP0222472A3 (en) 1989-11-29
JPH0468715B2 (de) 1992-11-04
EP0222472A2 (de) 1987-05-20
JPS6238591A (ja) 1987-02-19
DE3685871T2 (de) 1992-12-17
EP0222472B1 (de) 1992-07-01
KR900002621B1 (ko) 1990-04-20
US4862415A (en) 1989-08-29
KR870002653A (ko) 1987-04-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee