DE3671579D1 - Verfahren zur herstellung einer von einer isolierenden schicht bedeckten schicht aus einem feuerfesten metallsilizid auf einem substrat, insbesondere geeignet fuer die herstellung von schichten zur verbindung integrierter schaltungen. - Google Patents

Verfahren zur herstellung einer von einer isolierenden schicht bedeckten schicht aus einem feuerfesten metallsilizid auf einem substrat, insbesondere geeignet fuer die herstellung von schichten zur verbindung integrierter schaltungen.

Info

Publication number
DE3671579D1
DE3671579D1 DE8686400402T DE3671579T DE3671579D1 DE 3671579 D1 DE3671579 D1 DE 3671579D1 DE 8686400402 T DE8686400402 T DE 8686400402T DE 3671579 T DE3671579 T DE 3671579T DE 3671579 D1 DE3671579 D1 DE 3671579D1
Authority
DE
Germany
Prior art keywords
producing
substrate
metal silicide
layers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686400402T
Other languages
English (en)
Inventor
Alain Deneuville
Pierre Mandeville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Original Assignee
Centre National de la Recherche Scientifique CNRS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS filed Critical Centre National de la Recherche Scientifique CNRS
Application granted granted Critical
Publication of DE3671579D1 publication Critical patent/DE3671579D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/083—Ion implantation, general

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
DE8686400402T 1985-03-01 1986-02-25 Verfahren zur herstellung einer von einer isolierenden schicht bedeckten schicht aus einem feuerfesten metallsilizid auf einem substrat, insbesondere geeignet fuer die herstellung von schichten zur verbindung integrierter schaltungen. Expired - Fee Related DE3671579D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8503042A FR2578272B1 (fr) 1985-03-01 1985-03-01 Procede de formation sur un substrat d'une couche de siliciure de tungstene, utilisable notamment pour la realisation de couches d'interconnexion des circuits integres.

Publications (1)

Publication Number Publication Date
DE3671579D1 true DE3671579D1 (de) 1990-06-28

Family

ID=9316783

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686400402T Expired - Fee Related DE3671579D1 (de) 1985-03-01 1986-02-25 Verfahren zur herstellung einer von einer isolierenden schicht bedeckten schicht aus einem feuerfesten metallsilizid auf einem substrat, insbesondere geeignet fuer die herstellung von schichten zur verbindung integrierter schaltungen.

Country Status (6)

Country Link
US (1) US4777150A (de)
EP (1) EP0195700B1 (de)
JP (1) JPS61203636A (de)
AT (1) ATE53146T1 (de)
DE (1) DE3671579D1 (de)
FR (1) FR2578272B1 (de)

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* Cited by examiner, † Cited by third party
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JPS61214427A (ja) * 1985-03-19 1986-09-24 Nippon Gakki Seizo Kk 半導体装置の電極形成法
US4877748A (en) * 1987-05-01 1989-10-31 Texas Instruments Incorporated Bipolar process for forming shallow NPN emitters
KR900008868B1 (ko) * 1987-09-30 1990-12-11 삼성전자 주식회사 저항성 접촉을 갖는 반도체 장치의 제조방법
KR910005401B1 (ko) * 1988-09-07 1991-07-29 경상현 비결정 실리콘을 이용한 자기정렬 트랜지스터 제조방법
KR930007440B1 (ko) * 1989-02-02 1993-08-10 마쓰시다 덴끼 산고오 가부시기가이샤 고융점 금속 규소화물 박막을 가진 반도체 장치의 제조 방법
US5254874A (en) * 1990-05-02 1993-10-19 Quality Semiconductor Inc. High density local interconnect in a semiconductor circuit using metal silicide
US5223456A (en) * 1990-05-02 1993-06-29 Quality Semiconductor Inc. High density local interconnect in an integrated circit using metal silicide
US5443996A (en) * 1990-05-14 1995-08-22 At&T Global Information Solutions Company Process for forming titanium silicide local interconnect
JP2757927B2 (ja) * 1990-06-28 1998-05-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体基板上の隔置されたシリコン領域の相互接続方法
EP0463373A3 (en) * 1990-06-29 1992-03-25 Texas Instruments Incorporated Local interconnect using a material comprising tungsten
JPH04133313A (ja) * 1990-09-25 1992-05-07 Semiconductor Energy Lab Co Ltd 半導体作製方法
TW237562B (de) 1990-11-09 1995-01-01 Semiconductor Energy Res Co Ltd
US6979840B1 (en) * 1991-09-25 2005-12-27 Semiconductor Energy Laboratory Co., Ltd. Thin film transistors having anodized metal film between the gate wiring and drain wiring
JP3067433B2 (ja) * 1992-12-04 2000-07-17 キヤノン株式会社 半導体装置の製造方法
US5444302A (en) 1992-12-25 1995-08-22 Hitachi, Ltd. Semiconductor device including multi-layer conductive thin film of polycrystalline material
JPH06283612A (ja) * 1993-03-26 1994-10-07 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
US5510295A (en) * 1993-10-29 1996-04-23 International Business Machines Corporation Method for lowering the phase transformation temperature of a metal silicide
US5828131A (en) * 1993-10-29 1998-10-27 International Business Machines Corporation Low temperature formation of low resistivity titanium silicide
JP2720827B2 (ja) * 1994-07-05 1998-03-04 日本電気株式会社 半導体装置の製造方法
US5472896A (en) * 1994-11-14 1995-12-05 United Microelectronics Corp. Method for fabricating polycide gate MOSFET devices
JP2737764B2 (ja) * 1995-03-03 1998-04-08 日本電気株式会社 半導体装置及びその製造方法
KR0167242B1 (ko) * 1995-04-21 1998-12-15 구본준 게이트-드레인 중첩 소자의 제조 방법
US6187664B1 (en) * 1995-06-05 2001-02-13 Taiwan Semiconductor Manufacturing Company Method for forming a barrier metallization layer
US6096638A (en) * 1995-10-28 2000-08-01 Nec Corporation Method for forming a refractory metal silicide layer
TW396646B (en) 1997-09-11 2000-07-01 Lg Semicon Co Ltd Manufacturing method of semiconductor devices
KR100425147B1 (ko) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 반도체소자의제조방법
KR100255134B1 (ko) * 1997-12-31 2000-05-01 윤종용 반도체 장치 및 그 제조 방법
US5924001A (en) * 1998-01-08 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Ion implantation for preventing polycide void
US6277744B1 (en) 2000-01-21 2001-08-21 Advanced Micro Devices, Inc. Two-level silane nucleation for blanket tungsten deposition
US6284636B1 (en) * 2000-01-21 2001-09-04 Advanced Micro Devices, Inc. Tungsten gate method and apparatus
US6274472B1 (en) 2000-01-21 2001-08-14 Advanced Micro Devices, Inc. Tungsten interconnect method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5130437B1 (de) * 1970-03-25 1976-09-01
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4128670A (en) * 1977-11-11 1978-12-05 International Business Machines Corporation Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
US4263058A (en) * 1979-06-11 1981-04-21 General Electric Company Composite conductive structures in integrated circuits and method of making same
DE3027954A1 (de) * 1980-07-23 1982-02-25 Siemens AG, 1000 Berlin und 8000 München Integrierte mos-schaltung mit mindestens einer zusaetzlichen leiterbahnebene sowie ein verfahren zur herstellung derselben
US4337476A (en) * 1980-08-18 1982-06-29 Bell Telephone Laboratories, Incorporated Silicon rich refractory silicides as gate metal
US4339869A (en) * 1980-09-15 1982-07-20 General Electric Company Method of making low resistance contacts in semiconductor devices by ion induced silicides
GB2086135B (en) * 1980-09-30 1985-08-21 Nippon Telegraph & Telephone Electrode and semiconductor device provided with the electrode
US4398335A (en) * 1980-12-09 1983-08-16 Fairchild Camera & Instrument Corporation Multilayer metal silicide interconnections for integrated circuits
US4529619A (en) * 1984-07-16 1985-07-16 Xerox Corporation Ohmic contacts for hydrogenated amorphous silicon

Also Published As

Publication number Publication date
ATE53146T1 (de) 1990-06-15
EP0195700A1 (de) 1986-09-24
EP0195700B1 (de) 1990-05-23
FR2578272A1 (fr) 1986-09-05
JPS61203636A (ja) 1986-09-09
US4777150A (en) 1988-10-11
FR2578272B1 (fr) 1987-05-22

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee