DE3670546D1 - Verfahren zum herstellen einer halbleiteranordnung mit gegeneinander isolierten streifenfoermigen, sich gegenseitig ueberlappenden siliciumelektroden. - Google Patents

Verfahren zum herstellen einer halbleiteranordnung mit gegeneinander isolierten streifenfoermigen, sich gegenseitig ueberlappenden siliciumelektroden.

Info

Publication number
DE3670546D1
DE3670546D1 DE8686201549T DE3670546T DE3670546D1 DE 3670546 D1 DE3670546 D1 DE 3670546D1 DE 8686201549 T DE8686201549 T DE 8686201549T DE 3670546 T DE3670546 T DE 3670546T DE 3670546 D1 DE3670546 D1 DE 3670546D1
Authority
DE
Germany
Prior art keywords
strip
shaped
producing
semiconductor arrangement
electrodes overlapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686201549T
Other languages
English (en)
Inventor
Hermanus Leonardus Peek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3670546D1 publication Critical patent/DE3670546D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946Charge transfer devices
    • H01L29/66954Charge transfer devices with an insulated gate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/911Differential oxidation and etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8686201549T 1985-09-11 1986-09-09 Verfahren zum herstellen einer halbleiteranordnung mit gegeneinander isolierten streifenfoermigen, sich gegenseitig ueberlappenden siliciumelektroden. Expired - Lifetime DE3670546D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8502478A NL8502478A (nl) 1985-09-11 1985-09-11 Werkwijze ter vervaardiging van een halfgeleiderinrichting.

Publications (1)

Publication Number Publication Date
DE3670546D1 true DE3670546D1 (de) 1990-05-23

Family

ID=19846536

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686201549T Expired - Lifetime DE3670546D1 (de) 1985-09-11 1986-09-09 Verfahren zum herstellen einer halbleiteranordnung mit gegeneinander isolierten streifenfoermigen, sich gegenseitig ueberlappenden siliciumelektroden.

Country Status (5)

Country Link
US (1) US4700459A (de)
EP (1) EP0214702B1 (de)
JP (1) JPS6262544A (de)
DE (1) DE3670546D1 (de)
NL (1) NL8502478A (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04213975A (ja) * 1990-12-11 1992-08-05 Sony Corp 固体撮像装置
US5210049A (en) * 1992-04-28 1993-05-11 Eastman Kodak Company Method of making a solid state image sensor
TW218426B (de) * 1992-05-11 1994-01-01 Samsung Electronics Co Ltd
US6376868B1 (en) 1999-06-15 2002-04-23 Micron Technology, Inc. Multi-layered gate for a CMOS imager
US6654057B1 (en) * 1999-06-17 2003-11-25 Micron Technology, Inc. Active pixel sensor with a diagonal active area
US6326652B1 (en) 1999-06-18 2001-12-04 Micron Technology, Inc., CMOS imager with a self-aligned buried contact
US6414342B1 (en) 1999-06-18 2002-07-02 Micron Technology Inc. Photogate with improved short wavelength response for a CMOS imager
US6204524B1 (en) 1999-07-14 2001-03-20 Micron Technology, Inc. CMOS imager with storage capacitor
CN1323811C (zh) * 2003-04-29 2007-07-04 远藤工业株式会社 弹簧平衡器
JP2005079567A (ja) * 2003-09-04 2005-03-24 Matsushita Electric Ind Co Ltd 半導体装置、その製造方法およびカメラ
US20050274994A1 (en) * 2004-06-14 2005-12-15 Rhodes Howard E High dielectric constant spacer for imagers

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055885A (en) * 1973-02-28 1977-11-01 Hitachi, Ltd. Charge transfer semiconductor device with electrodes separated by oxide region therebetween and method for fabricating the same
US3909925A (en) * 1974-05-06 1975-10-07 Telex Computer Products N-Channel charge coupled device fabrication process
US3943543A (en) * 1974-07-26 1976-03-09 Texas Instruments Incorporated Three level electrode configuration for three phase charge coupled device
NL184591C (nl) * 1974-09-24 1989-09-01 Philips Nv Ladingsoverdrachtinrichting.
US4077112A (en) * 1974-09-24 1978-03-07 U.S. Philips Corporation Method of manufacturing charge transfer device
NL7709916A (nl) * 1977-09-09 1979-03-13 Philips Nv Ladingsgekoppelde inrichting.
US4262297A (en) * 1978-12-19 1981-04-14 The General Electric Company Limited Semiconductor charge transfer device with multi-level polysilicon electrode and bus-line structure
NL7907434A (nl) * 1979-10-08 1981-04-10 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting.
NL8202777A (nl) * 1982-07-09 1984-02-01 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen daarvan.

Also Published As

Publication number Publication date
NL8502478A (nl) 1987-04-01
EP0214702B1 (de) 1990-04-18
JPS6262544A (ja) 1987-03-19
EP0214702A1 (de) 1987-03-18
US4700459A (en) 1987-10-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee