DE3630605A1 - Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe - Google Patents

Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe

Info

Publication number
DE3630605A1
DE3630605A1 DE19863630605 DE3630605A DE3630605A1 DE 3630605 A1 DE3630605 A1 DE 3630605A1 DE 19863630605 DE19863630605 DE 19863630605 DE 3630605 A DE3630605 A DE 3630605A DE 3630605 A1 DE3630605 A1 DE 3630605A1
Authority
DE
Germany
Prior art keywords
output
inverted
input
inputs
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19863630605
Other languages
German (de)
English (en)
Other versions
DE3630605C2 (enrdf_load_stackoverflow
Inventor
Volkmar Dipl Ing Rebmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to DE19863630605 priority Critical patent/DE3630605A1/de
Publication of DE3630605A1 publication Critical patent/DE3630605A1/de
Application granted granted Critical
Publication of DE3630605C2 publication Critical patent/DE3630605C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4812—Multiplexers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE19863630605 1986-09-09 1986-09-09 Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe Granted DE3630605A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19863630605 DE3630605A1 (de) 1986-09-09 1986-09-09 Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19863630605 DE3630605A1 (de) 1986-09-09 1986-09-09 Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe

Publications (2)

Publication Number Publication Date
DE3630605A1 true DE3630605A1 (de) 1988-03-17
DE3630605C2 DE3630605C2 (enrdf_load_stackoverflow) 1989-05-24

Family

ID=6309185

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863630605 Granted DE3630605A1 (de) 1986-09-09 1986-09-09 Cmos-halbleiteranordnung als exor-nor-schaltung, insbesondere als baustein fuer eine cmos-volladdierstufe

Country Status (1)

Country Link
DE (1) DE3630605A1 (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2380739C1 (ru) * 2008-07-28 2010-01-27 Владимир Владимирович Шубин Сумматор
RU2408058C2 (ru) * 2009-03-23 2010-12-27 Владимир Владимирович Шубин Одноразрядный сумматор
RU2408922C1 (ru) * 2009-05-18 2011-01-10 Владимир Владимирович Шубин Одноразрядный двоичный сумматор

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0122946A1 (de) * 1983-04-15 1984-10-31 Deutsche ITT Industries GmbH CMOS-Volladdierstufe
US4523292A (en) * 1982-09-30 1985-06-11 Rca Corporation Complementary FET ripple carry binary adder circuit
US4547863A (en) * 1982-06-09 1985-10-15 International Standard Electric Corporation Integrated circuit three-input binary adder cell with high-speed sum propagation
US4564921A (en) * 1982-06-03 1986-01-14 Tokyo Shibaura Kenki Kabushiki Kaisha Full adder
US4583192A (en) * 1983-09-30 1986-04-15 Motorola, Inc. MOS full adder circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564921A (en) * 1982-06-03 1986-01-14 Tokyo Shibaura Kenki Kabushiki Kaisha Full adder
US4547863A (en) * 1982-06-09 1985-10-15 International Standard Electric Corporation Integrated circuit three-input binary adder cell with high-speed sum propagation
US4523292A (en) * 1982-09-30 1985-06-11 Rca Corporation Complementary FET ripple carry binary adder circuit
EP0122946A1 (de) * 1983-04-15 1984-10-31 Deutsche ITT Industries GmbH CMOS-Volladdierstufe
US4583192A (en) * 1983-09-30 1986-04-15 Motorola, Inc. MOS full adder circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2380739C1 (ru) * 2008-07-28 2010-01-27 Владимир Владимирович Шубин Сумматор
RU2408058C2 (ru) * 2009-03-23 2010-12-27 Владимир Владимирович Шубин Одноразрядный сумматор
RU2408922C1 (ru) * 2009-05-18 2011-01-10 Владимир Владимирович Шубин Одноразрядный двоичный сумматор

Also Published As

Publication number Publication date
DE3630605C2 (enrdf_load_stackoverflow) 1989-05-24

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Legal Events

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OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee