DE3577020D1 - Verfahren zur herstellung einer anordnung. - Google Patents

Verfahren zur herstellung einer anordnung.

Info

Publication number
DE3577020D1
DE3577020D1 DE8686900428T DE3577020T DE3577020D1 DE 3577020 D1 DE3577020 D1 DE 3577020D1 DE 8686900428 T DE8686900428 T DE 8686900428T DE 3577020 T DE3577020 T DE 3577020T DE 3577020 D1 DE3577020 D1 DE 3577020D1
Authority
DE
Germany
Prior art keywords
producing
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686900428T
Other languages
English (en)
Inventor
Bernard Alexander
Pang-Dow Foo
Joseph Schutz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of DE3577020D1 publication Critical patent/DE3577020D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
DE8686900428T 1984-12-18 1985-12-04 Verfahren zur herstellung einer anordnung. Expired - Fee Related DE3577020D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68277684A 1984-12-18 1984-12-18
PCT/US1985/002392 WO1986003887A2 (en) 1984-12-18 1985-12-04 Process for fabricating a device

Publications (1)

Publication Number Publication Date
DE3577020D1 true DE3577020D1 (de) 1990-05-10

Family

ID=24741091

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686900428T Expired - Fee Related DE3577020D1 (de) 1984-12-18 1985-12-04 Verfahren zur herstellung einer anordnung.

Country Status (9)

Country Link
EP (1) EP0205557B1 (de)
JP (1) JP2868764B2 (de)
KR (1) KR950000859B1 (de)
CA (1) CA1278768C (de)
DE (1) DE3577020D1 (de)
ES (1) ES8705704A1 (de)
IE (1) IE57062B1 (de)
SG (1) SG63690G (de)
WO (1) WO1986003887A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3629422C2 (de) * 1986-08-29 1994-02-17 Agfa Gevaert Ag Verfahren und Vorrichtung zum Einstellen von Belichtungsgrößen an einem Kopiergerät
US5089083A (en) * 1989-04-25 1992-02-18 Tokyo Electron Limited Plasma etching method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4427516A (en) * 1981-08-24 1984-01-24 Bell Telephone Laboratories, Incorporated Apparatus and method for plasma-assisted etching of wafers
US4397724A (en) * 1981-08-24 1983-08-09 Bell Telephone Laboratories, Incorporated Apparatus and method for plasma-assisted etching of wafers

Also Published As

Publication number Publication date
ES550034A0 (es) 1987-05-16
EP0205557A1 (de) 1986-12-30
CA1278768C (en) 1991-01-08
KR880700453A (ko) 1988-03-15
KR950000859B1 (ko) 1995-02-02
WO1986003887A2 (en) 1986-07-03
JPS62501183A (ja) 1987-05-07
JP2868764B2 (ja) 1999-03-10
ES8705704A1 (es) 1987-05-16
IE57062B1 (en) 1992-04-08
EP0205557B1 (de) 1990-04-04
WO1986003887A3 (en) 1986-08-14
SG63690G (en) 1990-09-07
IE853193L (en) 1986-06-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee