DE3381808D1 - Halbleiterspeichergeraet mit redundanzdecodierschaltung. - Google Patents

Halbleiterspeichergeraet mit redundanzdecodierschaltung.

Info

Publication number
DE3381808D1
DE3381808D1 DE8383303463T DE3381808T DE3381808D1 DE 3381808 D1 DE3381808 D1 DE 3381808D1 DE 8383303463 T DE8383303463 T DE 8383303463T DE 3381808 T DE3381808 T DE 3381808T DE 3381808 D1 DE3381808 D1 DE 3381808D1
Authority
DE
Germany
Prior art keywords
storage device
semiconductor storage
decoder circuit
redundancy decoder
redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383303463T
Other languages
German (de)
English (en)
Inventor
Mitsuo Higuchi
Ryoji Hagihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3381808D1 publication Critical patent/DE3381808D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
DE8383303463T 1982-06-30 1983-06-15 Halbleiterspeichergeraet mit redundanzdecodierschaltung. Expired - Lifetime DE3381808D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57111522A JPS593795A (ja) 1982-06-30 1982-06-30 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3381808D1 true DE3381808D1 (de) 1990-09-20

Family

ID=14563456

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383303463T Expired - Lifetime DE3381808D1 (de) 1982-06-30 1983-06-15 Halbleiterspeichergeraet mit redundanzdecodierschaltung.

Country Status (4)

Country Link
US (1) US4656609A (enExample)
EP (1) EP0098079B1 (enExample)
JP (1) JPS593795A (enExample)
DE (1) DE3381808D1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214399A (ja) * 1985-07-12 1987-01-22 Fujitsu Ltd 半導体記憶装置
JPH0668917B2 (ja) * 1987-05-15 1994-08-31 日本電気株式会社 メモリ素子入換制御回路
DE3728521A1 (de) * 1987-08-26 1989-03-09 Siemens Ag Anordnung und verfahren zur feststellung und lokalisierung von fehlerhaften schaltkreisen eines speicherbausteins
JP2785936B2 (ja) * 1988-04-12 1998-08-13 日本電気株式会社 冗長回路のテスト方法
IT1228166B (it) * 1988-10-06 1991-05-31 Sgs Thomson Microelectronics Circuito programmabile di selezione statica per dispositivi programmabili
DE69128746T2 (de) * 1990-06-19 1998-07-16 Texas Instruments Inc Laserstreckendecodierer für DRAM-Redundanzschema
JP3137993B2 (ja) * 1991-01-16 2001-02-26 富士通株式会社 不揮発性半導体記憶装置
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system
US5996106A (en) * 1997-02-04 1999-11-30 Micron Technology, Inc. Multi bank test mode for memory devices
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
US6078534A (en) * 1997-09-25 2000-06-20 Siemens Aktiengesellschaft Semiconductor memory having redundancy circuit
JP3701160B2 (ja) * 1999-12-24 2005-09-28 シャープ株式会社 冗長機能を有する不揮発性半導体メモリ装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128235A (en) * 1975-04-30 1976-11-09 Toshiba Corp A semi-conductor integration circuit memory
US4313106A (en) * 1980-06-30 1982-01-26 Rca Corporation Electrically programmable logic array
JPS57130298A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor integrated circuit memory and relieving method for its fault
US4489402A (en) * 1981-04-25 1984-12-18 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4422161A (en) * 1981-10-08 1983-12-20 Rca Corporation Memory array with redundant elements

Also Published As

Publication number Publication date
EP0098079B1 (en) 1990-08-16
EP0098079A2 (en) 1984-01-11
US4656609A (en) 1987-04-07
JPS6237477B2 (enExample) 1987-08-12
JPS593795A (ja) 1984-01-10
EP0098079A3 (en) 1987-04-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee