DE3177221D1 - Halbleiterspeicherschaltung. - Google Patents

Halbleiterspeicherschaltung.

Info

Publication number
DE3177221D1
DE3177221D1 DE8787104318T DE3177221T DE3177221D1 DE 3177221 D1 DE3177221 D1 DE 3177221D1 DE 8787104318 T DE8787104318 T DE 8787104318T DE 3177221 T DE3177221 T DE 3177221T DE 3177221 D1 DE3177221 D1 DE 3177221D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory circuit
circuit
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787104318T
Other languages
English (en)
Inventor
Yoshihiro Takemae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26478221&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3177221(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from JP55147773A external-priority patent/JPS5771580A/ja
Priority claimed from JP55147771A external-priority patent/JPS5771579A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3177221D1 publication Critical patent/DE3177221D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE8787104318T 1980-10-22 1981-10-22 Halbleiterspeicherschaltung. Expired - Lifetime DE3177221D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP55147773A JPS5771580A (en) 1980-10-22 1980-10-22 Semiconductor memory device
JP55147771A JPS5771579A (en) 1980-10-22 1980-10-22 Semiconductor memory device

Publications (1)

Publication Number Publication Date
DE3177221D1 true DE3177221D1 (de) 1990-11-15

Family

ID=26478221

Family Applications (2)

Application Number Title Priority Date Filing Date
DE8787104318T Expired - Lifetime DE3177221D1 (de) 1980-10-22 1981-10-22 Halbleiterspeicherschaltung.
DE8181304967T Expired DE3176601D1 (en) 1980-10-22 1981-10-22 Semiconductor memory circuit

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE8181304967T Expired DE3176601D1 (en) 1980-10-22 1981-10-22 Semiconductor memory circuit

Country Status (4)

Country Link
US (1) US4458336A (de)
EP (1) EP0050529B1 (de)
DE (2) DE3177221D1 (de)
IE (1) IE53512B1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617652A (en) * 1979-01-24 1986-10-14 Xicor, Inc. Integrated high voltage distribution and control systems
JPS58121195A (ja) * 1982-01-13 1983-07-19 Nec Corp プリチヤ−ジ信号発生回路
JPH0612619B2 (ja) * 1982-09-22 1994-02-16 株式会社日立製作所 半導体メモリ装置
JPS59121691A (ja) * 1982-12-01 1984-07-13 Fujitsu Ltd ダイナミツク型半導体記憶装置
US4584672A (en) * 1984-02-22 1986-04-22 Intel Corporation CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge
US4658382A (en) * 1984-07-11 1987-04-14 Texas Instruments Incorporated Dynamic memory with improved dummy cell circuitry
JPS6134619A (ja) * 1984-07-26 1986-02-18 Mitsubishi Electric Corp Ｍｏｓトランジスタ回路
JPS61158095A (ja) * 1984-12-28 1986-07-17 Toshiba Corp ダイナミツク型メモリのビツト線プリチヤ−ジ回路
EP0200500A3 (de) * 1985-04-26 1989-03-08 Advanced Micro Devices, Inc. CMOS-Speichervorspannungssystem
JPH01171194A (ja) * 1987-12-25 1989-07-06 Nec Ic Microcomput Syst Ltd 半導体記憶装置
US5687109A (en) * 1988-05-31 1997-11-11 Micron Technology, Inc. Integrated circuit module having on-chip surge capacitors
JPH0814995B2 (ja) * 1989-01-27 1996-02-14 株式会社東芝 半導体メモリ
GB9007787D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High-speed,small-swing datapath for dram
JPH05342873A (ja) * 1992-06-10 1993-12-24 Nec Corp 半導体記憶装置
JP3253745B2 (ja) * 1993-04-28 2002-02-04 富士通株式会社 半導体記憶装置
KR100214462B1 (ko) * 1995-11-27 1999-08-02 구본준 반도체메모리셀의 라이트 방법
US7145819B2 (en) * 2001-06-11 2006-12-05 Analog Devices, Inc. Method and apparatus for integrated circuit with DRAM
US9786345B1 (en) 2016-09-16 2017-10-10 Micron Technology, Inc. Compensation for threshold voltage variation of memory cell components

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4004284A (en) * 1975-03-05 1977-01-18 Teletype Corporation Binary voltage-differential sensing circuits, and sense/refresh amplifier circuits for random-access memories
US4045783A (en) * 1976-04-12 1977-08-30 Standard Microsystems Corporation Mos one transistor cell ram having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry
JPS54101230A (en) * 1978-01-26 1979-08-09 Nec Corp Dynamic mos memory circuit
US4195357A (en) * 1978-06-15 1980-03-25 Texas Instruments Incorporated Median spaced dummy cell layout for MOS random access memory
US4291393A (en) * 1980-02-11 1981-09-22 Mostek Corporation Active refresh circuit for dynamic MOS circuits

Also Published As

Publication number Publication date
US4458336A (en) 1984-07-03
EP0050529A3 (en) 1984-10-10
IE812483L (en) 1982-04-22
EP0050529A2 (de) 1982-04-28
DE3176601D1 (en) 1988-02-11
IE53512B1 (en) 1988-12-07
EP0050529B1 (de) 1988-01-07

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8366 Restricted maintained after opposition proceedings