DE3366554D1 - Programmable logic array according to the ecl technique - Google Patents
Programmable logic array according to the ecl techniqueInfo
- Publication number
- DE3366554D1 DE3366554D1 DE8383105129T DE3366554T DE3366554D1 DE 3366554 D1 DE3366554 D1 DE 3366554D1 DE 8383105129 T DE8383105129 T DE 8383105129T DE 3366554 T DE3366554 T DE 3366554T DE 3366554 D1 DE3366554 D1 DE 3366554D1
- Authority
- DE
- Germany
- Prior art keywords
- lines
- sum
- input
- programmable logic
- logic array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011159 matrix material Substances 0.000 abstract 3
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE8383105129T DE3366554D1 (en) | 1982-05-28 | 1983-05-24 | Programmable logic array according to the ecl technique |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3220302A DE3220302C2 (de) | 1982-05-28 | 1982-05-28 | Programmierbare Logikanordnung in ECL-Technik |
DE8383105129T DE3366554D1 (en) | 1982-05-28 | 1983-05-24 | Programmable logic array according to the ecl technique |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3366554D1 true DE3366554D1 (en) | 1986-11-06 |
Family
ID=6164838
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3220302A Expired DE3220302C2 (de) | 1982-05-28 | 1982-05-28 | Programmierbare Logikanordnung in ECL-Technik |
DE8383105129T Expired DE3366554D1 (en) | 1982-05-28 | 1983-05-24 | Programmable logic array according to the ecl technique |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3220302A Expired DE3220302C2 (de) | 1982-05-28 | 1982-05-28 | Programmierbare Logikanordnung in ECL-Technik |
Country Status (5)
Country | Link |
---|---|
US (1) | US4506363A (de) |
EP (1) | EP0095706B1 (de) |
JP (1) | JPS592440A (de) |
AT (1) | ATE22634T1 (de) |
DE (2) | DE3220302C2 (de) |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3958110A (en) * | 1974-12-18 | 1976-05-18 | Ibm Corporation | Logic array with testing circuitry |
US4225957A (en) * | 1978-10-16 | 1980-09-30 | International Business Machines Corporation | Testing macros embedded in LSI chips |
DE3064699D1 (en) * | 1979-08-21 | 1983-10-06 | Ibm | Large scale integrated programmable logic array |
JPS5693189A (en) * | 1979-12-18 | 1981-07-28 | Fujitsu Ltd | Field programable element |
DE2951946A1 (de) * | 1979-12-22 | 1981-07-02 | Ibm Deutschland Gmbh, 7000 Stuttgart | Fehlererkennungs- und -korrektureinrichtung fuer eine logische anordnung |
DE3015992A1 (de) * | 1980-04-25 | 1981-11-05 | Ibm Deutschland Gmbh, 7000 Stuttgart | Programmierbare logische anordnung |
US4404635A (en) * | 1981-03-27 | 1983-09-13 | International Business Machines Corporation | Programmable integrated circuit and method of testing the circuit before it is programmed |
US4435805A (en) * | 1981-06-04 | 1984-03-06 | International Business Machines Corporation | Testing of logic arrays |
US4410987B1 (en) * | 1981-07-13 | 1995-02-28 | Texas Instruments Inc | Preload test circuit for programmable logic arrays |
US4461000A (en) * | 1982-03-01 | 1984-07-17 | Harris Corporation | ROM/PLA Structure and method of testing |
-
1982
- 1982-05-28 DE DE3220302A patent/DE3220302C2/de not_active Expired
-
1983
- 1983-04-25 US US06/488,442 patent/US4506363A/en not_active Expired - Fee Related
- 1983-05-24 EP EP83105129A patent/EP0095706B1/de not_active Expired
- 1983-05-24 DE DE8383105129T patent/DE3366554D1/de not_active Expired
- 1983-05-24 AT AT83105129T patent/ATE22634T1/de not_active IP Right Cessation
- 1983-05-27 JP JP58093901A patent/JPS592440A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
US4506363A (en) | 1985-03-19 |
EP0095706B1 (de) | 1986-10-01 |
JPS592440A (ja) | 1984-01-09 |
DE3220302C2 (de) | 1984-03-15 |
JPH0239894B2 (de) | 1990-09-07 |
DE3220302A1 (de) | 1983-12-08 |
EP0095706A1 (de) | 1983-12-07 |
ATE22634T1 (de) | 1986-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE68918040D1 (de) | Integrierte Halbleiterschaltung mit Ein- und Ausgangsanschlüssen, die einen unabhängigen Verbindungstest erlauben. | |
KR880010573A (ko) | 대규모 반도체 논리장치 | |
KR900004252B1 (en) | Semiconductor integrated circuit | |
EP0098417A3 (de) | Halbleiterspeicheranordnung | |
DE3366554D1 (en) | Programmable logic array according to the ecl technique | |
GB1413217A (en) | Circuit for shifting the dc level of a signal | |
US5387810A (en) | Cell library for semiconductor integrated circuit design | |
DE3681666D1 (de) | Integrierter halbleiterspeicher. | |
JPS561545A (en) | Input/output buffer cell for semiconductor integrated circuit | |
ES380077A1 (es) | Circuitos de conversion de codigo en senales logicas. | |
JPS53107259A (en) | Compensator for delay of envelope | |
KR890016623A (ko) | 반도체 집적회로 장치 | |
KR920020718A (ko) | 신호 처리 장치 | |
JPS5684034A (en) | Logic circuit | |
GB1202137A (en) | Manufacture of integrated circuit | |
GB1330515A (en) | Connection between integrated circuit devices or the like | |
EP0395070A3 (de) | Integrierte Gattermatrixhalbleiterschaltung | |
JPS5681962A (en) | Preventing of crosstalk in semiconductor integrated circuit | |
JPS5757033A (en) | Logical operation circuit using complementary mis field effect transistor | |
KR930001224A (ko) | 반도체 기억 장치 | |
JPS55121746A (en) | Programmable logic array | |
JPS6426173A (en) | Integrated circuit | |
JPS5791552A (en) | Semiconductor integrated circuit device | |
JPS55123743A (en) | Logic integrated circuit easy to check | |
JPS54122966A (en) | Logic integrated circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |