JPS6426173A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS6426173A
JPS6426173A JP62183169A JP18316987A JPS6426173A JP S6426173 A JPS6426173 A JP S6426173A JP 62183169 A JP62183169 A JP 62183169A JP 18316987 A JP18316987 A JP 18316987A JP S6426173 A JPS6426173 A JP S6426173A
Authority
JP
Japan
Prior art keywords
circuits
circuit
testing
logic circuits
new
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183169A
Other languages
Japanese (ja)
Inventor
Katsumi Fujinami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62183169A priority Critical patent/JPS6426173A/en
Publication of JPS6426173A publication Critical patent/JPS6426173A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To test a new circuit, and also, to reduce the area of an integrated circuit by superposing a testing circuit on a new logic circuit substrate and a substrate for loading an IC-converted logic circuit, and connecting the testing circuit and input/output terminals of the IC-formed circuit. CONSTITUTION:Circuits 7-9 are provided on the same substrate 17 as new logic circuits 4-6, and LSI-converted logic circuits 1-3 are provided on a substrate 18. Also, input/output terminals of the logic circuits 1-3 and input/ output terminals of testing circuits 7-9 are connected physically by terminals 10-15. The testing circuits 7-9 are constituted of a tri-state buffer, and constituted so that its output goes to a high impedance except the test time, and the LSI-formed logic circuits 1-3 and the new logic circuits 4-6 are connected substantially, by a selecting signal terminal 112. Also, said circuits are constituted so that output signals of the new logic circuits 4-6 are returned to the new logic circuits 4-6 through the testing circuits 7-9, at the time of testing.
JP62183169A 1987-07-22 1987-07-22 Integrated circuit Pending JPS6426173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183169A JPS6426173A (en) 1987-07-22 1987-07-22 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183169A JPS6426173A (en) 1987-07-22 1987-07-22 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS6426173A true JPS6426173A (en) 1989-01-27

Family

ID=16130989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183169A Pending JPS6426173A (en) 1987-07-22 1987-07-22 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS6426173A (en)

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