DE3313335A1 - Daten-mehrfachleitungs-vorladeschaltung - Google Patents

Daten-mehrfachleitungs-vorladeschaltung

Info

Publication number
DE3313335A1
DE3313335A1 DE19833313335 DE3313335A DE3313335A1 DE 3313335 A1 DE3313335 A1 DE 3313335A1 DE 19833313335 DE19833313335 DE 19833313335 DE 3313335 A DE3313335 A DE 3313335A DE 3313335 A1 DE3313335 A1 DE 3313335A1
Authority
DE
Germany
Prior art keywords
circuit
data
precharge
line
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19833313335
Other languages
German (de)
English (en)
Other versions
DE3313335C2 (en, 2012
Inventor
Ryuichi Tokyo Iketani
Hiroshi Yokouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE3313335A1 publication Critical patent/DE3313335A1/de
Application granted granted Critical
Publication of DE3313335C2 publication Critical patent/DE3313335C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Microcomputers (AREA)
DE19833313335 1982-04-23 1983-04-13 Daten-mehrfachleitungs-vorladeschaltung Granted DE3313335A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57067452A JPS58186827A (ja) 1982-04-23 1982-04-23 マイクロプロセツサ

Publications (2)

Publication Number Publication Date
DE3313335A1 true DE3313335A1 (de) 1983-11-03
DE3313335C2 DE3313335C2 (en, 2012) 1989-10-12

Family

ID=13345327

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833313335 Granted DE3313335A1 (de) 1982-04-23 1983-04-13 Daten-mehrfachleitungs-vorladeschaltung

Country Status (4)

Country Link
US (1) US4551821A (en, 2012)
JP (1) JPS58186827A (en, 2012)
DE (1) DE3313335A1 (en, 2012)
GB (1) GB2121254B (en, 2012)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3533870A1 (de) * 1984-10-31 1986-04-30 Mitsubishi Denki K.K., Tokio/Tokyo Halbleiterspeichereinheit
EP0175526A3 (en) * 1984-09-06 1988-07-13 Oki Electric Industry Company, Limited Data bus discharging circuit
US6724672B2 (en) 2001-12-18 2004-04-20 Infineon Technologies Ag Integrated memory having a precharge circuit for precharging a bit line
DE19929121B4 (de) * 1998-06-30 2013-02-28 Fujitsu Semiconductor Ltd. Integrierte Halbleiterschaltung

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074034A (ja) * 1983-09-30 1985-04-26 Toshiba Corp パイプライン制御方式
JP2506767B2 (ja) * 1987-05-25 1996-06-12 松下電器産業株式会社 デ−タ保持装置
JPH01220016A (ja) * 1988-02-29 1989-09-01 Mitsubishi Electric Corp バス送出回路
KR920018591A (ko) * 1991-03-13 1992-10-22 제임스 에이취. 폭스 저파워 버스를 구비한 마이크로프로세서
IT1252017B (it) * 1991-11-28 1995-05-27 Sgs Thomson Microelectronics Struttura circuitale a registri distribuiti con lettura e scrittura autotemporizzate
KR0172345B1 (ko) * 1995-11-27 1999-03-30 김광호 반도체 메모리 장치의 하이퍼 페이지 모드의 데이터 출력신호 제어회로
DE19961727A1 (de) * 1999-12-21 2001-07-05 Micronas Gmbh Schaltungsanordnung mit einer Datenübertragungsvorrichtung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965460A (en) * 1975-01-02 1976-06-22 Motorola, Inc. MOS speed-up circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232014A (en) * 1975-09-05 1977-03-10 Hanamoto Kenkiyuushiyo Kk Method of coloring and moulding building articles
US4044341A (en) * 1976-03-22 1977-08-23 Rca Corporation Memory array
US4131951A (en) * 1976-05-17 1978-12-26 Tokyo Shibaura Electric Co., Ltd. High speed complementary MOS memory
JPS5687124A (en) * 1979-12-17 1981-07-15 Toshiba Corp Information processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965460A (en) * 1975-01-02 1976-06-22 Motorola, Inc. MOS speed-up circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Intel Corp., MCS-80/85 Family User's Manual, Oktober 1979, S. 6-80 bis 6-85 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175526A3 (en) * 1984-09-06 1988-07-13 Oki Electric Industry Company, Limited Data bus discharging circuit
DE3533870A1 (de) * 1984-10-31 1986-04-30 Mitsubishi Denki K.K., Tokio/Tokyo Halbleiterspeichereinheit
DE19929121B4 (de) * 1998-06-30 2013-02-28 Fujitsu Semiconductor Ltd. Integrierte Halbleiterschaltung
US6724672B2 (en) 2001-12-18 2004-04-20 Infineon Technologies Ag Integrated memory having a precharge circuit for precharging a bit line
DE10162260B4 (de) * 2001-12-18 2006-04-06 Infineon Technologies Ag Integrierter Speicher mit einer Vorladeschaltung zur Vorladung einer Bitleitung

Also Published As

Publication number Publication date
GB2121254A (en) 1983-12-14
DE3313335C2 (en, 2012) 1989-10-12
GB2121254B (en) 1986-03-12
JPS6244284B2 (en, 2012) 1987-09-19
US4551821A (en) 1985-11-05
JPS58186827A (ja) 1983-10-31
GB8309985D0 (en) 1983-05-18

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8363 Opposition against the patent
8328 Change in the person/name/address of the agent

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